A low power and small area all digital delay-locked loop based on ring oscillator architecture

Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain...
Ausführliche Beschreibung

Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. Ausführliche Beschreibung