Design of carrier tracking loop for Beidou receiver based on SoC FPGA
In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FP...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Wei Zhaochuan [verfasserIn] Pan Jundao [verfasserIn] Wu Guozeng [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Chinesisch |
| Erschienen: |
2018 |
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| Schlagwörter: |
Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA |
|---|
| Übergeordnetes Werk: |
In: Dianzi Jishu Yingyong - National Computer System Engineering Research Institute of China, 2018, 44(2018), 6, Seite 124-128 |
|---|---|
| Übergeordnetes Werk: |
volume:44 ; year:2018 ; number:6 ; pages:124-128 |
| Links: |
|---|
| DOI / URN: |
10.16157/j.issn.0258-7998.173766 |
|---|
| Katalog-ID: |
DOAJ001309331 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | DOAJ001309331 | ||
| 003 | DE-627 | ||
| 005 | 20230309162410.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 230225s2018 xx |||||o 00| ||chi c | ||
| 024 | 7 | |a 10.16157/j.issn.0258-7998.173766 |2 doi | |
| 035 | |a (DE-627)DOAJ001309331 | ||
| 035 | |a (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a chi | ||
| 050 | 0 | |a TK7800-8360 | |
| 100 | 0 | |a Wei Zhaochuan |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| 264 | 1 | |c 2018 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. | ||
| 650 | 4 | |a Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA | |
| 653 | 0 | |a Electronics | |
| 700 | 0 | |a Pan Jundao |e verfasserin |4 aut | |
| 700 | 0 | |a Wu Guozeng |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i In |t Dianzi Jishu Yingyong |d National Computer System Engineering Research Institute of China, 2018 |g 44(2018), 6, Seite 124-128 |w (DE-627)1760603147 |x 02587998 |7 nnns |
| 773 | 1 | 8 | |g volume:44 |g year:2018 |g number:6 |g pages:124-128 |
| 856 | 4 | 0 | |u https://doi.org/10.16157/j.issn.0258-7998.173766 |z kostenfrei |
| 856 | 4 | 0 | |u https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 |z kostenfrei |
| 856 | 4 | 0 | |u http://www.chinaaet.com/article/3000084546 |z kostenfrei |
| 856 | 4 | 2 | |u https://doaj.org/toc/0258-7998 |y Journal toc |z kostenfrei |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_DOAJ | ||
| 951 | |a AR | ||
| 952 | |d 44 |j 2018 |e 6 |h 124-128 | ||
| author_variant |
w z wz p j pj w g wg |
|---|---|
| matchkey_str |
article:02587998:2018----::einfaretaknlofredueev |
| hierarchy_sort_str |
2018 |
| callnumber-subject-code |
TK |
| publishDate |
2018 |
| allfields |
10.16157/j.issn.0258-7998.173766 doi (DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 DE-627 ger DE-627 rakwb chi TK7800-8360 Wei Zhaochuan verfasserin aut Design of carrier tracking loop for Beidou receiver based on SoC FPGA 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics Pan Jundao verfasserin aut Wu Guozeng verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 44(2018), 6, Seite 124-128 (DE-627)1760603147 02587998 nnns volume:44 year:2018 number:6 pages:124-128 https://doi.org/10.16157/j.issn.0258-7998.173766 kostenfrei https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 kostenfrei http://www.chinaaet.com/article/3000084546 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 44 2018 6 124-128 |
| spelling |
10.16157/j.issn.0258-7998.173766 doi (DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 DE-627 ger DE-627 rakwb chi TK7800-8360 Wei Zhaochuan verfasserin aut Design of carrier tracking loop for Beidou receiver based on SoC FPGA 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics Pan Jundao verfasserin aut Wu Guozeng verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 44(2018), 6, Seite 124-128 (DE-627)1760603147 02587998 nnns volume:44 year:2018 number:6 pages:124-128 https://doi.org/10.16157/j.issn.0258-7998.173766 kostenfrei https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 kostenfrei http://www.chinaaet.com/article/3000084546 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 44 2018 6 124-128 |
| allfields_unstemmed |
10.16157/j.issn.0258-7998.173766 doi (DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 DE-627 ger DE-627 rakwb chi TK7800-8360 Wei Zhaochuan verfasserin aut Design of carrier tracking loop for Beidou receiver based on SoC FPGA 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics Pan Jundao verfasserin aut Wu Guozeng verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 44(2018), 6, Seite 124-128 (DE-627)1760603147 02587998 nnns volume:44 year:2018 number:6 pages:124-128 https://doi.org/10.16157/j.issn.0258-7998.173766 kostenfrei https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 kostenfrei http://www.chinaaet.com/article/3000084546 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 44 2018 6 124-128 |
| allfieldsGer |
10.16157/j.issn.0258-7998.173766 doi (DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 DE-627 ger DE-627 rakwb chi TK7800-8360 Wei Zhaochuan verfasserin aut Design of carrier tracking loop for Beidou receiver based on SoC FPGA 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics Pan Jundao verfasserin aut Wu Guozeng verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 44(2018), 6, Seite 124-128 (DE-627)1760603147 02587998 nnns volume:44 year:2018 number:6 pages:124-128 https://doi.org/10.16157/j.issn.0258-7998.173766 kostenfrei https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 kostenfrei http://www.chinaaet.com/article/3000084546 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 44 2018 6 124-128 |
| allfieldsSound |
10.16157/j.issn.0258-7998.173766 doi (DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 DE-627 ger DE-627 rakwb chi TK7800-8360 Wei Zhaochuan verfasserin aut Design of carrier tracking loop for Beidou receiver based on SoC FPGA 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics Pan Jundao verfasserin aut Wu Guozeng verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 44(2018), 6, Seite 124-128 (DE-627)1760603147 02587998 nnns volume:44 year:2018 number:6 pages:124-128 https://doi.org/10.16157/j.issn.0258-7998.173766 kostenfrei https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 kostenfrei http://www.chinaaet.com/article/3000084546 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 44 2018 6 124-128 |
| language |
Chinese |
| source |
In Dianzi Jishu Yingyong 44(2018), 6, Seite 124-128 volume:44 year:2018 number:6 pages:124-128 |
| sourceStr |
In Dianzi Jishu Yingyong 44(2018), 6, Seite 124-128 volume:44 year:2018 number:6 pages:124-128 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA Electronics |
| isfreeaccess_bool |
true |
| container_title |
Dianzi Jishu Yingyong |
| authorswithroles_txt_mv |
Wei Zhaochuan @@aut@@ Pan Jundao @@aut@@ Wu Guozeng @@aut@@ |
| publishDateDaySort_date |
2018-01-01T00:00:00Z |
| hierarchy_top_id |
1760603147 |
| id |
DOAJ001309331 |
| language_de |
chinesisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ001309331</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230309162410.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">230225s2018 xx |||||o 00| ||chi c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.16157/j.issn.0258-7998.173766</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ001309331</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">chi</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7800-8360</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Wei Zhaochuan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of carrier tracking loop for Beidou receiver based on SoC FPGA</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2018</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electronics</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Pan Jundao</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Wu Guozeng</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Dianzi Jishu Yingyong</subfield><subfield code="d">National Computer System Engineering Research Institute of China, 2018</subfield><subfield code="g">44(2018), 6, Seite 124-128</subfield><subfield code="w">(DE-627)1760603147</subfield><subfield code="x">02587998</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:44</subfield><subfield code="g">year:2018</subfield><subfield code="g">number:6</subfield><subfield code="g">pages:124-128</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.16157/j.issn.0258-7998.173766</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.chinaaet.com/article/3000084546</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/0258-7998</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">44</subfield><subfield code="j">2018</subfield><subfield code="e">6</subfield><subfield code="h">124-128</subfield></datafield></record></collection>
|
| callnumber-first |
T - Technology |
| author |
Wei Zhaochuan |
| spellingShingle |
Wei Zhaochuan misc TK7800-8360 misc Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA misc Electronics Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| authorStr |
Wei Zhaochuan |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)1760603147 |
| format |
electronic Article |
| delete_txt_mv |
keep |
| author_role |
aut aut aut |
| collection |
DOAJ |
| remote_str |
true |
| callnumber-label |
TK7800-8360 |
| illustrated |
Not Illustrated |
| issn |
02587998 |
| topic_title |
TK7800-8360 Design of carrier tracking loop for Beidou receiver based on SoC FPGA Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA |
| topic |
misc TK7800-8360 misc Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA misc Electronics |
| topic_unstemmed |
misc TK7800-8360 misc Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA misc Electronics |
| topic_browse |
misc TK7800-8360 misc Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA misc Electronics |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
Dianzi Jishu Yingyong |
| hierarchy_parent_id |
1760603147 |
| hierarchy_top_title |
Dianzi Jishu Yingyong |
| isfreeaccess_txt |
true |
| familylinks_str_mv |
(DE-627)1760603147 |
| title |
Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| ctrlnum |
(DE-627)DOAJ001309331 (DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7 |
| title_full |
Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| author_sort |
Wei Zhaochuan |
| journal |
Dianzi Jishu Yingyong |
| journalStr |
Dianzi Jishu Yingyong |
| callnumber-first-code |
T |
| lang_code |
chi |
| isOA_bool |
true |
| recordtype |
marc |
| publishDateSort |
2018 |
| contenttype_str_mv |
txt |
| container_start_page |
124 |
| author_browse |
Wei Zhaochuan Pan Jundao Wu Guozeng |
| container_volume |
44 |
| class |
TK7800-8360 |
| format_se |
Elektronische Aufsätze |
| author-letter |
Wei Zhaochuan |
| doi_str_mv |
10.16157/j.issn.0258-7998.173766 |
| author2-role |
verfasserin |
| title_sort |
design of carrier tracking loop for beidou receiver based on soc fpga |
| callnumber |
TK7800-8360 |
| title_auth |
Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| abstract |
In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. |
| abstractGer |
In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. |
| abstract_unstemmed |
In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ |
| container_issue |
6 |
| title_short |
Design of carrier tracking loop for Beidou receiver based on SoC FPGA |
| url |
https://doi.org/10.16157/j.issn.0258-7998.173766 https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7 http://www.chinaaet.com/article/3000084546 https://doaj.org/toc/0258-7998 |
| remote_bool |
true |
| author2 |
Pan Jundao Wu Guozeng |
| author2Str |
Pan Jundao Wu Guozeng |
| ppnlink |
1760603147 |
| callnumber-subject |
TK - Electrical and Nuclear Engineering |
| mediatype_str_mv |
c |
| isOA_txt |
true |
| hochschulschrift_bool |
false |
| doi_str |
10.16157/j.issn.0258-7998.173766 |
| callnumber-a |
TK7800-8360 |
| up_date |
2024-07-03T19:39:41.960Z |
| _version_ |
1803588030392434689 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ001309331</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230309162410.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">230225s2018 xx |||||o 00| ||chi c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.16157/j.issn.0258-7998.173766</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ001309331</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJad98c89a1e3b467e9292e5fbc84d10d7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">chi</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7800-8360</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Wei Zhaochuan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of carrier tracking loop for Beidou receiver based on SoC FPGA</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2018</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">In order to realize the high real-time, miniaturization and low power consumption of Beidou satellite navigation receiver, a design scheme of carrier tracking loop based on SoC FPGA is proposed. Through the analysis of FLL and PLL, and using SOPC technology, the carrier tracking loop based on SoC FPGA is realized, and the carrier can be completely stripped inside the FPGA. The test results show that the scheme can realize fast and accurate tracking of carrier signals, and has good real-time and application value.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Beidou satellite navigation receiver; carrier tracking loop; SoC FPGA</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electronics</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Pan Jundao</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Wu Guozeng</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Dianzi Jishu Yingyong</subfield><subfield code="d">National Computer System Engineering Research Institute of China, 2018</subfield><subfield code="g">44(2018), 6, Seite 124-128</subfield><subfield code="w">(DE-627)1760603147</subfield><subfield code="x">02587998</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:44</subfield><subfield code="g">year:2018</subfield><subfield code="g">number:6</subfield><subfield code="g">pages:124-128</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.16157/j.issn.0258-7998.173766</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/ad98c89a1e3b467e9292e5fbc84d10d7</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.chinaaet.com/article/3000084546</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/0258-7998</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">44</subfield><subfield code="j">2018</subfield><subfield code="e">6</subfield><subfield code="h">124-128</subfield></datafield></record></collection>
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| score |
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