Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-me...
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Autor*in:	Zongxian Yang [verfasserIn] Kangqiang Pan [verfasserIn] Norman Y. Zhou [verfasserIn] Lan Wei [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2022

Schlagwörter:	3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann

Übergeordnetes Werk:	In: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits - IEEE, 2019, 8(2022), 2, Seite 84-92
Übergeordnetes Werk:	volume:8 ; year:2022 ; number:2 ; pages:84-92

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.1109/JXCDC.2022.3206778

Katalog-ID:	DOAJ009980083

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allfields	10.1109/JXCDC.2022.3206778 doi (DE-627)DOAJ009980083 (DE-599)DOAJ2daa069e8aad4af4b6378a7f9c05c1bd DE-627 ger DE-627 rakwb eng TK7885-7895 Zongxian Yang verfasserin aut Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified. 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann Computer engineering. Computer hardware Kangqiang Pan verfasserin aut Norman Y. Zhou verfasserin aut Lan Wei verfasserin aut In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE, 2019 8(2022), 2, Seite 84-92 (DE-627)842240136 (DE-600)2840841-X 23299231 nnns volume:8 year:2022 number:2 pages:84-92 https://doi.org/10.1109/JXCDC.2022.3206778 kostenfrei https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd kostenfrei https://ieeexplore.ieee.org/document/9893161/ kostenfrei https://doaj.org/toc/2329-9231 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_187 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2190 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2022 2 84-92
spelling	10.1109/JXCDC.2022.3206778 doi (DE-627)DOAJ009980083 (DE-599)DOAJ2daa069e8aad4af4b6378a7f9c05c1bd DE-627 ger DE-627 rakwb eng TK7885-7895 Zongxian Yang verfasserin aut Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified. 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann Computer engineering. Computer hardware Kangqiang Pan verfasserin aut Norman Y. Zhou verfasserin aut Lan Wei verfasserin aut In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE, 2019 8(2022), 2, Seite 84-92 (DE-627)842240136 (DE-600)2840841-X 23299231 nnns volume:8 year:2022 number:2 pages:84-92 https://doi.org/10.1109/JXCDC.2022.3206778 kostenfrei https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd kostenfrei https://ieeexplore.ieee.org/document/9893161/ kostenfrei https://doaj.org/toc/2329-9231 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_187 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2190 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2022 2 84-92
allfields_unstemmed	10.1109/JXCDC.2022.3206778 doi (DE-627)DOAJ009980083 (DE-599)DOAJ2daa069e8aad4af4b6378a7f9c05c1bd DE-627 ger DE-627 rakwb eng TK7885-7895 Zongxian Yang verfasserin aut Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified. 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann Computer engineering. Computer hardware Kangqiang Pan verfasserin aut Norman Y. Zhou verfasserin aut Lan Wei verfasserin aut In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE, 2019 8(2022), 2, Seite 84-92 (DE-627)842240136 (DE-600)2840841-X 23299231 nnns volume:8 year:2022 number:2 pages:84-92 https://doi.org/10.1109/JXCDC.2022.3206778 kostenfrei https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd kostenfrei https://ieeexplore.ieee.org/document/9893161/ kostenfrei https://doaj.org/toc/2329-9231 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_187 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2190 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2022 2 84-92
allfieldsGer	10.1109/JXCDC.2022.3206778 doi (DE-627)DOAJ009980083 (DE-599)DOAJ2daa069e8aad4af4b6378a7f9c05c1bd DE-627 ger DE-627 rakwb eng TK7885-7895 Zongxian Yang verfasserin aut Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified. 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann Computer engineering. Computer hardware Kangqiang Pan verfasserin aut Norman Y. Zhou verfasserin aut Lan Wei verfasserin aut In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE, 2019 8(2022), 2, Seite 84-92 (DE-627)842240136 (DE-600)2840841-X 23299231 nnns volume:8 year:2022 number:2 pages:84-92 https://doi.org/10.1109/JXCDC.2022.3206778 kostenfrei https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd kostenfrei https://ieeexplore.ieee.org/document/9893161/ kostenfrei https://doaj.org/toc/2329-9231 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_187 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2190 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2022 2 84-92
allfieldsSound	10.1109/JXCDC.2022.3206778 doi (DE-627)DOAJ009980083 (DE-599)DOAJ2daa069e8aad4af4b6378a7f9c05c1bd DE-627 ger DE-627 rakwb eng TK7885-7895 Zongxian Yang verfasserin aut Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified. 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann Computer engineering. Computer hardware Kangqiang Pan verfasserin aut Norman Y. Zhou verfasserin aut Lan Wei verfasserin aut In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE, 2019 8(2022), 2, Seite 84-92 (DE-627)842240136 (DE-600)2840841-X 23299231 nnns volume:8 year:2022 number:2 pages:84-92 https://doi.org/10.1109/JXCDC.2022.3206778 kostenfrei https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd kostenfrei https://ieeexplore.ieee.org/document/9893161/ kostenfrei https://doaj.org/toc/2329-9231 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_187 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2190 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2022 2 84-92
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callnumber-first	T - Technology
author	Zongxian Yang
spellingShingle	Zongxian Yang misc TK7885-7895 misc 3-D memory array misc concurrent computation misc in-memory computing misc memory architecture misc non-volatile memory misc non-von Neumann misc Computer engineering. Computer hardware Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
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topic_title	TK7885-7895 Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays 3-D memory array concurrent computation in-memory computing memory architecture non-volatile memory non-von Neumann
topic	misc TK7885-7895 misc 3-D memory array misc concurrent computation misc in-memory computing misc memory architecture misc non-volatile memory misc non-von Neumann misc Computer engineering. Computer hardware
topic_unstemmed	misc TK7885-7895 misc 3-D memory array misc concurrent computation misc in-memory computing misc memory architecture misc non-volatile memory misc non-von Neumann misc Computer engineering. Computer hardware
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title	Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
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title_sort	scalable 2t2r logic computation structure: design from digital logic circuits to 3-d stacked memory arrays
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title_auth	Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
abstract	In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.
abstractGer	In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.
abstract_unstemmed	In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.
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title_short	Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
url	https://doi.org/10.1109/JXCDC.2022.3206778 https://doaj.org/article/2daa069e8aad4af4b6378a7f9c05c1bd https://ieeexplore.ieee.org/document/9893161/ https://doaj.org/toc/2329-9231
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up_date	2024-07-04T01:47:28.107Z
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