Design and implementation of PCIe on UM-BUS test system
The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisit...
Ausführliche Beschreibung
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| Autor*in: |
Sun Fengxia [verfasserIn] Zhang Weigong [verfasserIn] Zhou Jiqin [verfasserIn] Wang Ying [verfasserIn] |
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E-Artikel |
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| Sprache: |
Chinesisch |
| Erschienen: |
2019 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
In: Dianzi Jishu Yingyong - National Computer System Engineering Research Institute of China, 2018, 45(2019), 5, Seite 61-65 |
|---|---|
| Übergeordnetes Werk: |
volume:45 ; year:2019 ; number:5 ; pages:61-65 |
| Links: |
|---|
| DOI / URN: |
10.16157/j.issn.0258-7998.190034 |
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DOAJ010744452 |
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| 520 | |a The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. | ||
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10.16157/j.issn.0258-7998.190034 doi (DE-627)DOAJ010744452 (DE-599)DOAJc95ce48c055a4403adea3a5a1a8d26e1 DE-627 ger DE-627 rakwb chi TK7800-8360 Sun Fengxia verfasserin aut Design and implementation of PCIe on UM-BUS test system 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. UM-BUS bus test system PCIe bus BMD data communication Electronics Zhang Weigong verfasserin aut Zhou Jiqin verfasserin aut Wang Ying verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 45(2019), 5, Seite 61-65 (DE-627)1760603147 02587998 nnns volume:45 year:2019 number:5 pages:61-65 https://doi.org/10.16157/j.issn.0258-7998.190034 kostenfrei https://doaj.org/article/c95ce48c055a4403adea3a5a1a8d26e1 kostenfrei http://www.chinaaet.com/article/3000101516 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 45 2019 5 61-65 |
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10.16157/j.issn.0258-7998.190034 doi (DE-627)DOAJ010744452 (DE-599)DOAJc95ce48c055a4403adea3a5a1a8d26e1 DE-627 ger DE-627 rakwb chi TK7800-8360 Sun Fengxia verfasserin aut Design and implementation of PCIe on UM-BUS test system 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. UM-BUS bus test system PCIe bus BMD data communication Electronics Zhang Weigong verfasserin aut Zhou Jiqin verfasserin aut Wang Ying verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 45(2019), 5, Seite 61-65 (DE-627)1760603147 02587998 nnns volume:45 year:2019 number:5 pages:61-65 https://doi.org/10.16157/j.issn.0258-7998.190034 kostenfrei https://doaj.org/article/c95ce48c055a4403adea3a5a1a8d26e1 kostenfrei http://www.chinaaet.com/article/3000101516 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 45 2019 5 61-65 |
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10.16157/j.issn.0258-7998.190034 doi (DE-627)DOAJ010744452 (DE-599)DOAJc95ce48c055a4403adea3a5a1a8d26e1 DE-627 ger DE-627 rakwb chi TK7800-8360 Sun Fengxia verfasserin aut Design and implementation of PCIe on UM-BUS test system 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. UM-BUS bus test system PCIe bus BMD data communication Electronics Zhang Weigong verfasserin aut Zhou Jiqin verfasserin aut Wang Ying verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 45(2019), 5, Seite 61-65 (DE-627)1760603147 02587998 nnns volume:45 year:2019 number:5 pages:61-65 https://doi.org/10.16157/j.issn.0258-7998.190034 kostenfrei https://doaj.org/article/c95ce48c055a4403adea3a5a1a8d26e1 kostenfrei http://www.chinaaet.com/article/3000101516 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 45 2019 5 61-65 |
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10.16157/j.issn.0258-7998.190034 doi (DE-627)DOAJ010744452 (DE-599)DOAJc95ce48c055a4403adea3a5a1a8d26e1 DE-627 ger DE-627 rakwb chi TK7800-8360 Sun Fengxia verfasserin aut Design and implementation of PCIe on UM-BUS test system 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. UM-BUS bus test system PCIe bus BMD data communication Electronics Zhang Weigong verfasserin aut Zhou Jiqin verfasserin aut Wang Ying verfasserin aut In Dianzi Jishu Yingyong National Computer System Engineering Research Institute of China, 2018 45(2019), 5, Seite 61-65 (DE-627)1760603147 02587998 nnns volume:45 year:2019 number:5 pages:61-65 https://doi.org/10.16157/j.issn.0258-7998.190034 kostenfrei https://doaj.org/article/c95ce48c055a4403adea3a5a1a8d26e1 kostenfrei http://www.chinaaet.com/article/3000101516 kostenfrei https://doaj.org/toc/0258-7998 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 45 2019 5 61-65 |
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The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. |
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The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. |
| abstract_unstemmed |
The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system. |
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TK - Electrical and Nuclear Engineering |
| mediatype_str_mv |
c |
| isOA_txt |
true |
| hochschulschrift_bool |
false |
| doi_str |
10.16157/j.issn.0258-7998.190034 |
| callnumber-a |
TK7800-8360 |
| up_date |
2024-07-03T16:31:41.407Z |
| _version_ |
1803576201872146432 |
| fullrecord_marcxml |
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7.4007006 |