An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation

Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving opera...
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Autor*in:	Song-Nien Tang [verfasserIn] Jen-Chien Liao [verfasserIn] Chen-Kai Chiu [verfasserIn] Pei-Tong Ku [verfasserIn] Yen-Shuo Chen [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	Booth multiplier fixed-width truncation error compensation bit-width adaptive

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 10(2021), 20, p 2511
Übergeordnetes Werk:	volume:10 ; year:2021 ; number:20, p 2511

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics10202511

Katalog-ID:	DOAJ023798238

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520			\|a Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.
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spelling	10.3390/electronics10202511 doi (DE-627)DOAJ023798238 (DE-599)DOAJc477d3c2c6164ff8b41ad948469c65e0 DE-627 ger DE-627 rakwb eng TK7800-8360 Song-Nien Tang verfasserin aut An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration. Booth multiplier fixed-width truncation error compensation bit-width adaptive Electronics Jen-Chien Liao verfasserin aut Chen-Kai Chiu verfasserin aut Pei-Tong Ku verfasserin aut Yen-Shuo Chen verfasserin aut In Electronics MDPI AG, 2013 10(2021), 20, p 2511 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:20, p 2511 https://doi.org/10.3390/electronics10202511 kostenfrei https://doaj.org/article/c477d3c2c6164ff8b41ad948469c65e0 kostenfrei https://www.mdpi.com/2079-9292/10/20/2511 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 20, p 2511
allfields_unstemmed	10.3390/electronics10202511 doi (DE-627)DOAJ023798238 (DE-599)DOAJc477d3c2c6164ff8b41ad948469c65e0 DE-627 ger DE-627 rakwb eng TK7800-8360 Song-Nien Tang verfasserin aut An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration. Booth multiplier fixed-width truncation error compensation bit-width adaptive Electronics Jen-Chien Liao verfasserin aut Chen-Kai Chiu verfasserin aut Pei-Tong Ku verfasserin aut Yen-Shuo Chen verfasserin aut In Electronics MDPI AG, 2013 10(2021), 20, p 2511 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:20, p 2511 https://doi.org/10.3390/electronics10202511 kostenfrei https://doaj.org/article/c477d3c2c6164ff8b41ad948469c65e0 kostenfrei https://www.mdpi.com/2079-9292/10/20/2511 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 20, p 2511
allfieldsGer	10.3390/electronics10202511 doi (DE-627)DOAJ023798238 (DE-599)DOAJc477d3c2c6164ff8b41ad948469c65e0 DE-627 ger DE-627 rakwb eng TK7800-8360 Song-Nien Tang verfasserin aut An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration. Booth multiplier fixed-width truncation error compensation bit-width adaptive Electronics Jen-Chien Liao verfasserin aut Chen-Kai Chiu verfasserin aut Pei-Tong Ku verfasserin aut Yen-Shuo Chen verfasserin aut In Electronics MDPI AG, 2013 10(2021), 20, p 2511 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:20, p 2511 https://doi.org/10.3390/electronics10202511 kostenfrei https://doaj.org/article/c477d3c2c6164ff8b41ad948469c65e0 kostenfrei https://www.mdpi.com/2079-9292/10/20/2511 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 20, p 2511
allfieldsSound	10.3390/electronics10202511 doi (DE-627)DOAJ023798238 (DE-599)DOAJc477d3c2c6164ff8b41ad948469c65e0 DE-627 ger DE-627 rakwb eng TK7800-8360 Song-Nien Tang verfasserin aut An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration. Booth multiplier fixed-width truncation error compensation bit-width adaptive Electronics Jen-Chien Liao verfasserin aut Chen-Kai Chiu verfasserin aut Pei-Tong Ku verfasserin aut Yen-Shuo Chen verfasserin aut In Electronics MDPI AG, 2013 10(2021), 20, p 2511 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:20, p 2511 https://doi.org/10.3390/electronics10202511 kostenfrei https://doaj.org/article/c477d3c2c6164ff8b41ad948469c65e0 kostenfrei https://www.mdpi.com/2079-9292/10/20/2511 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 20, p 2511
language	English
source	In Electronics 10(2021), 20, p 2511 volume:10 year:2021 number:20, p 2511
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topic_facet	Booth multiplier fixed-width truncation error compensation bit-width adaptive Electronics
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authorswithroles_txt_mv	Song-Nien Tang @@aut@@ Jen-Chien Liao @@aut@@ Chen-Kai Chiu @@aut@@ Pei-Tong Ku @@aut@@ Yen-Shuo Chen @@aut@@
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callnumber-first	T - Technology
author	Song-Nien Tang
spellingShingle	Song-Nien Tang misc TK7800-8360 misc Booth multiplier misc fixed-width misc truncation error compensation misc bit-width adaptive misc Electronics An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
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topic_title	TK7800-8360 An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation Booth multiplier fixed-width truncation error compensation bit-width adaptive
topic	misc TK7800-8360 misc Booth multiplier misc fixed-width misc truncation error compensation misc bit-width adaptive misc Electronics
topic_unstemmed	misc TK7800-8360 misc Booth multiplier misc fixed-width misc truncation error compensation misc bit-width adaptive misc Electronics
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title	An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
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title_full	An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
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title_sort	accuracy-improved fixed-width booth multiplier enabling bit-width adaptive truncation error compensation
callnumber	TK7800-8360
title_auth	An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
abstract	Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.
abstractGer	Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.
abstract_unstemmed	Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple <i<L</i<′-bit numerical ranges of input data for an <i<L</i<-bit FWBM (<i<L′ ≤ L</i<). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.
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title_short	An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
url	https://doi.org/10.3390/electronics10202511 https://doaj.org/article/c477d3c2c6164ff8b41ad948469c65e0 https://www.mdpi.com/2079-9292/10/20/2511 https://doaj.org/toc/2079-9292
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author2	Jen-Chien Liao Chen-Kai Chiu Pei-Tong Ku Yen-Shuo Chen
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up_date	2024-07-03T19:32:35.398Z
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