2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR i...
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Autor*in:	Jihyun Baek [verfasserIn] Juyong Lee [verfasserIn] Jintae Kim [verfasserIn] Hyungil Chae [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2022

Schlagwörter:	analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 11(2022), 19, p 3072
Übergeordnetes Werk:	volume:11 ; year:2022 ; number:19, p 3072

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics11193072

Katalog-ID:	DOAJ028286057

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520			\|a This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.
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allfields	10.3390/electronics11193072 doi (DE-627)DOAJ028286057 (DE-599)DOAJ5a9934bc373f4361b0ebd9200151219b DE-627 ger DE-627 rakwb eng TK7800-8360 Jihyun Baek verfasserin aut 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics Juyong Lee verfasserin aut Jintae Kim verfasserin aut Hyungil Chae verfasserin aut In Electronics MDPI AG, 2013 11(2022), 19, p 3072 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:11 year:2022 number:19, p 3072 https://doi.org/10.3390/electronics11193072 kostenfrei https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b kostenfrei https://www.mdpi.com/2079-9292/11/19/3072 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 11 2022 19, p 3072
spelling	10.3390/electronics11193072 doi (DE-627)DOAJ028286057 (DE-599)DOAJ5a9934bc373f4361b0ebd9200151219b DE-627 ger DE-627 rakwb eng TK7800-8360 Jihyun Baek verfasserin aut 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics Juyong Lee verfasserin aut Jintae Kim verfasserin aut Hyungil Chae verfasserin aut In Electronics MDPI AG, 2013 11(2022), 19, p 3072 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:11 year:2022 number:19, p 3072 https://doi.org/10.3390/electronics11193072 kostenfrei https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b kostenfrei https://www.mdpi.com/2079-9292/11/19/3072 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 11 2022 19, p 3072
allfields_unstemmed	10.3390/electronics11193072 doi (DE-627)DOAJ028286057 (DE-599)DOAJ5a9934bc373f4361b0ebd9200151219b DE-627 ger DE-627 rakwb eng TK7800-8360 Jihyun Baek verfasserin aut 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics Juyong Lee verfasserin aut Jintae Kim verfasserin aut Hyungil Chae verfasserin aut In Electronics MDPI AG, 2013 11(2022), 19, p 3072 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:11 year:2022 number:19, p 3072 https://doi.org/10.3390/electronics11193072 kostenfrei https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b kostenfrei https://www.mdpi.com/2079-9292/11/19/3072 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 11 2022 19, p 3072
allfieldsGer	10.3390/electronics11193072 doi (DE-627)DOAJ028286057 (DE-599)DOAJ5a9934bc373f4361b0ebd9200151219b DE-627 ger DE-627 rakwb eng TK7800-8360 Jihyun Baek verfasserin aut 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics Juyong Lee verfasserin aut Jintae Kim verfasserin aut Hyungil Chae verfasserin aut In Electronics MDPI AG, 2013 11(2022), 19, p 3072 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:11 year:2022 number:19, p 3072 https://doi.org/10.3390/electronics11193072 kostenfrei https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b kostenfrei https://www.mdpi.com/2079-9292/11/19/3072 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 11 2022 19, p 3072
allfieldsSound	10.3390/electronics11193072 doi (DE-627)DOAJ028286057 (DE-599)DOAJ5a9934bc373f4361b0ebd9200151219b DE-627 ger DE-627 rakwb eng TK7800-8360 Jihyun Baek verfasserin aut 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics Juyong Lee verfasserin aut Jintae Kim verfasserin aut Hyungil Chae verfasserin aut In Electronics MDPI AG, 2013 11(2022), 19, p 3072 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:11 year:2022 number:19, p 3072 https://doi.org/10.3390/electronics11193072 kostenfrei https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b kostenfrei https://www.mdpi.com/2079-9292/11/19/3072 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 11 2022 19, p 3072
language	English
source	In Electronics 11(2022), 19, p 3072 volume:11 year:2022 number:19, p 3072
sourceStr	In Electronics 11(2022), 19, p 3072 volume:11 year:2022 number:19, p 3072
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier Electronics
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container_title	Electronics
authorswithroles_txt_mv	Jihyun Baek @@aut@@ Juyong Lee @@aut@@ Jintae Kim @@aut@@ Hyungil Chae @@aut@@
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callnumber-first	T - Technology
author	Jihyun Baek
spellingShingle	Jihyun Baek misc TK7800-8360 misc analog-to-digital converter misc noise-shaping misc pipelined SAR ADC misc pipelined noise-shaping SAR ADC misc ring amplifier misc Electronics 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure
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topic_title	TK7800-8360 2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure analog-to-digital converter noise-shaping pipelined SAR ADC pipelined noise-shaping SAR ADC ring amplifier
topic	misc TK7800-8360 misc analog-to-digital converter misc noise-shaping misc pipelined SAR ADC misc pipelined noise-shaping SAR ADC misc ring amplifier misc Electronics
topic_unstemmed	misc TK7800-8360 misc analog-to-digital converter misc noise-shaping misc pipelined SAR ADC misc pipelined noise-shaping SAR ADC misc ring amplifier misc Electronics
topic_browse	misc TK7800-8360 misc analog-to-digital converter misc noise-shaping misc pipelined SAR ADC misc pipelined noise-shaping SAR ADC misc ring amplifier misc Electronics
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title	2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure
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title_full	2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure
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journal	Electronics
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author_browse	Jihyun Baek Juyong Lee Jintae Kim Hyungil Chae
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title_sort	2nd-order pipelined noise-shaping sar adc using error-feedback structure
callnumber	TK7800-8360
title_auth	2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure
abstract	This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.
abstractGer	This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.
abstract_unstemmed	This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<msub<<mrow<<mi<FoM</mi<</mrow<<mrow<<mrow<<mi mathvariant="normal"<S</mi<<mo<,</mo<<mi<SNDR</mi<</mrow<</mrow<</msub<</mrow<</semantics<</math<</inline-formula< is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.
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title_short	2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure
url	https://doi.org/10.3390/electronics11193072 https://doaj.org/article/5a9934bc373f4361b0ebd9200151219b https://www.mdpi.com/2079-9292/11/19/3072 https://doaj.org/toc/2079-9292
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author2	Juyong Lee Jintae Kim Hyungil Chae
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doi_str	10.3390/electronics11193072
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