Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Lorenzo Benvenuti [verfasserIn] Alessandro Catania [verfasserIn] Giuseppe Manfredini [verfasserIn] Andrea Ria [verfasserIn] Massimo Piotto [verfasserIn] Paolo Bruschi [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 10(2021), 10, p 1156
Übergeordnetes Werk:	volume:10 ; year:2021 ; number:10, p 1156

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics10101156

Katalog-ID:	DOAJ029888239

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allfields	10.3390/electronics10101156 doi (DE-627)DOAJ029888239 (DE-599)DOAJ8ecbe50179d540cda80a3367f08d883a DE-627 ger DE-627 rakwb eng TK7800-8360 Lorenzo Benvenuti verfasserin aut Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics Alessandro Catania verfasserin aut Giuseppe Manfredini verfasserin aut Andrea Ria verfasserin aut Massimo Piotto verfasserin aut Paolo Bruschi verfasserin aut In Electronics MDPI AG, 2013 10(2021), 10, p 1156 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:10, p 1156 https://doi.org/10.3390/electronics10101156 kostenfrei https://doaj.org/article/8ecbe50179d540cda80a3367f08d883a kostenfrei https://www.mdpi.com/2079-9292/10/10/1156 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 10, p 1156
spelling	10.3390/electronics10101156 doi (DE-627)DOAJ029888239 (DE-599)DOAJ8ecbe50179d540cda80a3367f08d883a DE-627 ger DE-627 rakwb eng TK7800-8360 Lorenzo Benvenuti verfasserin aut Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics Alessandro Catania verfasserin aut Giuseppe Manfredini verfasserin aut Andrea Ria verfasserin aut Massimo Piotto verfasserin aut Paolo Bruschi verfasserin aut In Electronics MDPI AG, 2013 10(2021), 10, p 1156 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:10, p 1156 https://doi.org/10.3390/electronics10101156 kostenfrei https://doaj.org/article/8ecbe50179d540cda80a3367f08d883a kostenfrei https://www.mdpi.com/2079-9292/10/10/1156 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 10, p 1156
allfields_unstemmed	10.3390/electronics10101156 doi (DE-627)DOAJ029888239 (DE-599)DOAJ8ecbe50179d540cda80a3367f08d883a DE-627 ger DE-627 rakwb eng TK7800-8360 Lorenzo Benvenuti verfasserin aut Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics Alessandro Catania verfasserin aut Giuseppe Manfredini verfasserin aut Andrea Ria verfasserin aut Massimo Piotto verfasserin aut Paolo Bruschi verfasserin aut In Electronics MDPI AG, 2013 10(2021), 10, p 1156 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:10, p 1156 https://doi.org/10.3390/electronics10101156 kostenfrei https://doaj.org/article/8ecbe50179d540cda80a3367f08d883a kostenfrei https://www.mdpi.com/2079-9292/10/10/1156 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 10, p 1156
allfieldsGer	10.3390/electronics10101156 doi (DE-627)DOAJ029888239 (DE-599)DOAJ8ecbe50179d540cda80a3367f08d883a DE-627 ger DE-627 rakwb eng TK7800-8360 Lorenzo Benvenuti verfasserin aut Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics Alessandro Catania verfasserin aut Giuseppe Manfredini verfasserin aut Andrea Ria verfasserin aut Massimo Piotto verfasserin aut Paolo Bruschi verfasserin aut In Electronics MDPI AG, 2013 10(2021), 10, p 1156 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:10, p 1156 https://doi.org/10.3390/electronics10101156 kostenfrei https://doaj.org/article/8ecbe50179d540cda80a3367f08d883a kostenfrei https://www.mdpi.com/2079-9292/10/10/1156 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 10, p 1156
allfieldsSound	10.3390/electronics10101156 doi (DE-627)DOAJ029888239 (DE-599)DOAJ8ecbe50179d540cda80a3367f08d883a DE-627 ger DE-627 rakwb eng TK7800-8360 Lorenzo Benvenuti verfasserin aut Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics Alessandro Catania verfasserin aut Giuseppe Manfredini verfasserin aut Andrea Ria verfasserin aut Massimo Piotto verfasserin aut Paolo Bruschi verfasserin aut In Electronics MDPI AG, 2013 10(2021), 10, p 1156 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:10, p 1156 https://doi.org/10.3390/electronics10101156 kostenfrei https://doaj.org/article/8ecbe50179d540cda80a3367f08d883a kostenfrei https://www.mdpi.com/2079-9292/10/10/1156 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 10, p 1156
language	English
source	In Electronics 10(2021), 10, p 1156 volume:10 year:2021 number:10, p 1156
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topic_facet	ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage Electronics
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authorswithroles_txt_mv	Lorenzo Benvenuti @@aut@@ Alessandro Catania @@aut@@ Giuseppe Manfredini @@aut@@ Andrea Ria @@aut@@ Massimo Piotto @@aut@@ Paolo Bruschi @@aut@@
publishDateDaySort_date	2021-01-01T00:00:00Z
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callnumber-first	T - Technology
author	Lorenzo Benvenuti
spellingShingle	Lorenzo Benvenuti misc TK7800-8360 misc ADC misc delta-sigma modulator misc energy-harvesting misc inverter-like misc ultra-low power misc ultra-low voltage misc Electronics Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
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topic_title	TK7800-8360 Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage
topic	misc TK7800-8360 misc ADC misc delta-sigma modulator misc energy-harvesting misc inverter-like misc ultra-low power misc ultra-low voltage misc Electronics
topic_unstemmed	misc TK7800-8360 misc ADC misc delta-sigma modulator misc energy-harvesting misc inverter-like misc ultra-low power misc ultra-low voltage misc Electronics
topic_browse	misc TK7800-8360 misc ADC misc delta-sigma modulator misc energy-harvesting misc inverter-like misc ultra-low power misc ultra-low voltage misc Electronics
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title	Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
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title_full	Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
author_sort	Lorenzo Benvenuti
journal	Electronics
journalStr	Electronics
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lang_code	eng
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publishDateSort	2021
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author_browse	Lorenzo Benvenuti Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi
container_volume	10
class	TK7800-8360
format_se	Elektronische Aufsätze
author-letter	Lorenzo Benvenuti
doi_str_mv	10.3390/electronics10101156
author2-role	verfasserin
title_sort	design strategies and architectures for ultra-low-voltage delta-sigma adcs
callnumber	TK7800-8360
title_auth	Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
abstract	The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.
abstractGer	The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.
abstract_unstemmed	The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi mathvariant="sans-serif"<Δ</mi<<mi mathvariant="sans-serif"<Σ</mi<</mrow<</semantics<</math<</inline-formula< modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup<TM</sup< design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.
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title_short	Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
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author2	Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi
author2Str	Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi
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