Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. T...
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Autor*in:	Waldemar Jendernalik [verfasserIn] Jacek Jakusz [verfasserIn] Robert Piotrowski [verfasserIn] Grzegorz Blakiewicz [verfasserIn] Stanisław Szczepański [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 10(2021), 14, p 1613
Übergeordnetes Werk:	volume:10 ; year:2021 ; number:14, p 1613

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics10141613

Katalog-ID:	DOAJ030407664

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520			\|a A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).
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spelling	10.3390/electronics10141613 doi (DE-627)DOAJ030407664 (DE-599)DOAJ932a3ebf0abb4101a8205b7fc7799a22 DE-627 ger DE-627 rakwb eng TK7800-8360 Waldemar Jendernalik verfasserin aut Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB). CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits Electronics Jacek Jakusz verfasserin aut Robert Piotrowski verfasserin aut Grzegorz Blakiewicz verfasserin aut Stanisław Szczepański verfasserin aut In Electronics MDPI AG, 2013 10(2021), 14, p 1613 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:14, p 1613 https://doi.org/10.3390/electronics10141613 kostenfrei https://doaj.org/article/932a3ebf0abb4101a8205b7fc7799a22 kostenfrei https://www.mdpi.com/2079-9292/10/14/1613 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 14, p 1613
allfields_unstemmed	10.3390/electronics10141613 doi (DE-627)DOAJ030407664 (DE-599)DOAJ932a3ebf0abb4101a8205b7fc7799a22 DE-627 ger DE-627 rakwb eng TK7800-8360 Waldemar Jendernalik verfasserin aut Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB). CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits Electronics Jacek Jakusz verfasserin aut Robert Piotrowski verfasserin aut Grzegorz Blakiewicz verfasserin aut Stanisław Szczepański verfasserin aut In Electronics MDPI AG, 2013 10(2021), 14, p 1613 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:14, p 1613 https://doi.org/10.3390/electronics10141613 kostenfrei https://doaj.org/article/932a3ebf0abb4101a8205b7fc7799a22 kostenfrei https://www.mdpi.com/2079-9292/10/14/1613 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 14, p 1613
allfieldsGer	10.3390/electronics10141613 doi (DE-627)DOAJ030407664 (DE-599)DOAJ932a3ebf0abb4101a8205b7fc7799a22 DE-627 ger DE-627 rakwb eng TK7800-8360 Waldemar Jendernalik verfasserin aut Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB). CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits Electronics Jacek Jakusz verfasserin aut Robert Piotrowski verfasserin aut Grzegorz Blakiewicz verfasserin aut Stanisław Szczepański verfasserin aut In Electronics MDPI AG, 2013 10(2021), 14, p 1613 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:14, p 1613 https://doi.org/10.3390/electronics10141613 kostenfrei https://doaj.org/article/932a3ebf0abb4101a8205b7fc7799a22 kostenfrei https://www.mdpi.com/2079-9292/10/14/1613 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 14, p 1613
allfieldsSound	10.3390/electronics10141613 doi (DE-627)DOAJ030407664 (DE-599)DOAJ932a3ebf0abb4101a8205b7fc7799a22 DE-627 ger DE-627 rakwb eng TK7800-8360 Waldemar Jendernalik verfasserin aut Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB). CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits Electronics Jacek Jakusz verfasserin aut Robert Piotrowski verfasserin aut Grzegorz Blakiewicz verfasserin aut Stanisław Szczepański verfasserin aut In Electronics MDPI AG, 2013 10(2021), 14, p 1613 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:10 year:2021 number:14, p 1613 https://doi.org/10.3390/electronics10141613 kostenfrei https://doaj.org/article/932a3ebf0abb4101a8205b7fc7799a22 kostenfrei https://www.mdpi.com/2079-9292/10/14/1613 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 10 2021 14, p 1613
language	English
source	In Electronics 10(2021), 14, p 1613 volume:10 year:2021 number:14, p 1613
sourceStr	In Electronics 10(2021), 14, p 1613 volume:10 year:2021 number:14, p 1613
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits Electronics
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authorswithroles_txt_mv	Waldemar Jendernalik @@aut@@ Jacek Jakusz @@aut@@ Robert Piotrowski @@aut@@ Grzegorz Blakiewicz @@aut@@ Stanisław Szczepański @@aut@@
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callnumber-first	T - Technology
author	Waldemar Jendernalik
spellingShingle	Waldemar Jendernalik misc TK7800-8360 misc CMOS analogue circuits misc buffer amplifier misc unity-gain voltage amplifier misc CMOS integrated circuits misc Electronics Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path
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topic_title	TK7800-8360 Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path CMOS analogue circuits buffer amplifier unity-gain voltage amplifier CMOS integrated circuits
topic	misc TK7800-8360 misc CMOS analogue circuits misc buffer amplifier misc unity-gain voltage amplifier misc CMOS integrated circuits misc Electronics
topic_unstemmed	misc TK7800-8360 misc CMOS analogue circuits misc buffer amplifier misc unity-gain voltage amplifier misc CMOS integrated circuits misc Electronics
topic_browse	misc TK7800-8360 misc CMOS analogue circuits misc buffer amplifier misc unity-gain voltage amplifier misc CMOS integrated circuits misc Electronics
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title	Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path
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title_sort	unity-gain zero-offset cmos buffer with improved feedforward path
callnumber	TK7800-8360
title_auth	Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path
abstract	A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).
abstractGer	A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).
abstract_unstemmed	A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm<sup<2</sup<), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).
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title_short	Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path
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up_date	2024-07-03T14:50:03.079Z
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