A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Shi Zuo [verfasserIn] Jianzhong Zhao [verfasserIn] Yumei Zhou [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	SSPLL hybrid dual path loop low jitter low power consumption

Übergeordnetes Werk:	In: Sensors - MDPI AG, 2003, 21(2021), 22, p 7648
Übergeordnetes Werk:	volume:21 ; year:2021 ; number:22, p 7648

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/s21227648

Katalog-ID:	DOAJ03103070X

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allfields	10.3390/s21227648 doi (DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40 DE-627 ger DE-627 rakwb eng TP1-1185 Shi Zuo verfasserin aut A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM. SSPLL hybrid dual path loop low jitter low power consumption Chemical technology Jianzhong Zhao verfasserin aut Yumei Zhou verfasserin aut In Sensors MDPI AG, 2003 21(2021), 22, p 7648 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:21 year:2021 number:22, p 7648 https://doi.org/10.3390/s21227648 kostenfrei https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 kostenfrei https://www.mdpi.com/1424-8220/21/22/7648 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 21 2021 22, p 7648
spelling	10.3390/s21227648 doi (DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40 DE-627 ger DE-627 rakwb eng TP1-1185 Shi Zuo verfasserin aut A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM. SSPLL hybrid dual path loop low jitter low power consumption Chemical technology Jianzhong Zhao verfasserin aut Yumei Zhou verfasserin aut In Sensors MDPI AG, 2003 21(2021), 22, p 7648 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:21 year:2021 number:22, p 7648 https://doi.org/10.3390/s21227648 kostenfrei https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 kostenfrei https://www.mdpi.com/1424-8220/21/22/7648 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 21 2021 22, p 7648
allfields_unstemmed	10.3390/s21227648 doi (DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40 DE-627 ger DE-627 rakwb eng TP1-1185 Shi Zuo verfasserin aut A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM. SSPLL hybrid dual path loop low jitter low power consumption Chemical technology Jianzhong Zhao verfasserin aut Yumei Zhou verfasserin aut In Sensors MDPI AG, 2003 21(2021), 22, p 7648 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:21 year:2021 number:22, p 7648 https://doi.org/10.3390/s21227648 kostenfrei https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 kostenfrei https://www.mdpi.com/1424-8220/21/22/7648 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 21 2021 22, p 7648
allfieldsGer	10.3390/s21227648 doi (DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40 DE-627 ger DE-627 rakwb eng TP1-1185 Shi Zuo verfasserin aut A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM. SSPLL hybrid dual path loop low jitter low power consumption Chemical technology Jianzhong Zhao verfasserin aut Yumei Zhou verfasserin aut In Sensors MDPI AG, 2003 21(2021), 22, p 7648 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:21 year:2021 number:22, p 7648 https://doi.org/10.3390/s21227648 kostenfrei https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 kostenfrei https://www.mdpi.com/1424-8220/21/22/7648 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 21 2021 22, p 7648
allfieldsSound	10.3390/s21227648 doi (DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40 DE-627 ger DE-627 rakwb eng TP1-1185 Shi Zuo verfasserin aut A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM. SSPLL hybrid dual path loop low jitter low power consumption Chemical technology Jianzhong Zhao verfasserin aut Yumei Zhou verfasserin aut In Sensors MDPI AG, 2003 21(2021), 22, p 7648 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:21 year:2021 number:22, p 7648 https://doi.org/10.3390/s21227648 kostenfrei https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 kostenfrei https://www.mdpi.com/1424-8220/21/22/7648 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 21 2021 22, p 7648
language	English
source	In Sensors 21(2021), 22, p 7648 volume:21 year:2021 number:22, p 7648
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authorswithroles_txt_mv	Shi Zuo @@aut@@ Jianzhong Zhao @@aut@@ Yumei Zhou @@aut@@
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callnumber-first	T - Technology
author	Shi Zuo
spellingShingle	Shi Zuo misc TP1-1185 misc SSPLL misc hybrid dual path loop misc low jitter misc low power consumption misc Chemical technology A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM
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callnumber-label	TP1-1185
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issn	14248220
topic_title	TP1-1185 A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM SSPLL hybrid dual path loop low jitter low power consumption
topic	misc TP1-1185 misc SSPLL misc hybrid dual path loop misc low jitter misc low power consumption misc Chemical technology
topic_unstemmed	misc TP1-1185 misc SSPLL misc hybrid dual path loop misc low jitter misc low power consumption misc Chemical technology
topic_browse	misc TP1-1185 misc SSPLL misc hybrid dual path loop misc low jitter misc low power consumption misc Chemical technology
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title	A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM
ctrlnum	(DE-627)DOAJ03103070X (DE-599)DOAJ1362c36475e14fa1bfb6e948908c7f40
title_full	A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM
author_sort	Shi Zuo
journal	Sensors
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author_browse	Shi Zuo Jianzhong Zhao Yumei Zhou
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format_se	Elektronische Aufsätze
author-letter	Shi Zuo
doi_str_mv	10.3390/s21227648
author2-role	verfasserin
title_sort	0.8 v, 5.3–5.9 ghz sub-sampling pll with 196.5 fs<sub<<i<rms</i<</sub< integrated jitter and −251.6 db fom
callnumber	TP1-1185
title_auth	A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM
abstract	This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM.
abstractGer	This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM.
abstract_unstemmed	This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mo<−</mo<<mn<251.6</mn<</mrow<</semantics<</math<</inline-formula< dB FoM.
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container_issue	22, p 7648
title_short	A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM
url	https://doi.org/10.3390/s21227648 https://doaj.org/article/1362c36475e14fa1bfb6e948908c7f40 https://www.mdpi.com/1424-8220/21/22/7648 https://doaj.org/toc/1424-8220
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doi_str	10.3390/s21227648
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up_date	2024-07-03T18:22:32.310Z
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A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub<<i<rms</i<</sub< Integrated Jitter and −251.6 dB FoM

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