Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing

Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold va...
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Autor*in:	Esther Lee [verfasserIn] Tae Hyeon Kim [verfasserIn] Seung Won Lee [verfasserIn] Jee Hoon Kim [verfasserIn] Jaeun Kim [verfasserIn] Tae Gun Jeong [verfasserIn] Ji-Hoon Ahn [verfasserIn] Byungjin Cho [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2019

Schlagwörter:	Indium gallium zinc oxide IGZO Post annealing Capacitance–voltage measurement X-ray photoelectron spectroscopy depth profiling Electrical bias stress stability

Übergeordnetes Werk:	In: Nano Convergence - SpringerOpen, 2015, 6(2019), 1, Seite 8
Übergeordnetes Werk:	volume:6 ; year:2019 ; number:1 ; pages:8

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.1186/s40580-019-0194-1

Katalog-ID:	DOAJ036356956

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520			\|a Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor.
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topic_facet	Indium gallium zinc oxide IGZO Post annealing Capacitance–voltage measurement X-ray photoelectron spectroscopy depth profiling Electrical bias stress stability Technology T Chemical technology Biotechnology Science Q Physics
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authorswithroles_txt_mv	Esther Lee @@aut@@ Tae Hyeon Kim @@aut@@ Seung Won Lee @@aut@@ Jee Hoon Kim @@aut@@ Jaeun Kim @@aut@@ Tae Gun Jeong @@aut@@ Ji-Hoon Ahn @@aut@@ Byungjin Cho @@aut@@
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callnumber-first	T - Technology
author	Esther Lee
spellingShingle	Esther Lee misc TP1-1185 misc TP248.13-248.65 misc QC1-999 misc Indium gallium zinc oxide IGZO misc Post annealing misc Capacitance–voltage measurement misc X-ray photoelectron spectroscopy depth profiling misc Electrical bias stress stability misc Technology misc T misc Chemical technology misc Biotechnology misc Science misc Q misc Physics Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
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topic_title	TP1-1185 TP248.13-248.65 QC1-999 Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing Indium gallium zinc oxide IGZO Post annealing Capacitance–voltage measurement X-ray photoelectron spectroscopy depth profiling Electrical bias stress stability
topic	misc TP1-1185 misc TP248.13-248.65 misc QC1-999 misc Indium gallium zinc oxide IGZO misc Post annealing misc Capacitance–voltage measurement misc X-ray photoelectron spectroscopy depth profiling misc Electrical bias stress stability misc Technology misc T misc Chemical technology misc Biotechnology misc Science misc Q misc Physics
topic_unstemmed	misc TP1-1185 misc TP248.13-248.65 misc QC1-999 misc Indium gallium zinc oxide IGZO misc Post annealing misc Capacitance–voltage measurement misc X-ray photoelectron spectroscopy depth profiling misc Electrical bias stress stability misc Technology misc T misc Chemical technology misc Biotechnology misc Science misc Q misc Physics
topic_browse	misc TP1-1185 misc TP248.13-248.65 misc QC1-999 misc Indium gallium zinc oxide IGZO misc Post annealing misc Capacitance–voltage measurement misc X-ray photoelectron spectroscopy depth profiling misc Electrical bias stress stability misc Technology misc T misc Chemical technology misc Biotechnology misc Science misc Q misc Physics
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title	Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
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title_full	Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
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title_sort	improved electrical performance of a sol–gel igzo transistor with high-k al2o3 gate dielectric achieved by post annealing
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title_auth	Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
abstract	Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor.
abstractGer	Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor.
abstract_unstemmed	Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor.
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title_short	Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
url	https://doi.org/10.1186/s40580-019-0194-1 https://doaj.org/article/5a91faa09b684f3f9b8a48e31950e624 http://link.springer.com/article/10.1186/s40580-019-0194-1 https://doaj.org/toc/2196-5404
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author2	Tae Hyeon Kim Seung Won Lee Jee Hoon Kim Jaeun Kim Tae Gun Jeong Ji-Hoon Ahn Byungjin Cho
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up_date	2024-07-03T20:08:04.839Z
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The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. 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Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing

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