Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications

Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles...
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Autor*in:	Yi Tian [verfasserIn] Haifeng Hu [verfasserIn] Peipei Chen [verfasserIn] Fengliang Dong [verfasserIn] Hui Huang [verfasserIn] Lihua Xu [verfasserIn] Lanqin Yan [verfasserIn] Zhiwei Song [verfasserIn] Taoran Xu [verfasserIn] Weiguo Chu [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2022

Schlagwörter:	batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection

Übergeordnetes Werk:	In: Advanced Science - Wiley, 2015, 9(2022), 15, Seite n/a-n/a
Übergeordnetes Werk:	volume:9 ; year:2022 ; number:15 ; pages:n/a-n/a

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.1002/advs.202200647

Katalog-ID:	DOAJ042757517

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520			\|a Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.
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700	0		\|a Hui Huang \|e verfasserin \|4 aut
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700	0		\|a Lanqin Yan \|e verfasserin \|4 aut
700	0		\|a Zhiwei Song \|e verfasserin \|4 aut
700	0		\|a Taoran Xu \|e verfasserin \|4 aut
700	0		\|a Weiguo Chu \|e verfasserin \|4 aut
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allfields	10.1002/advs.202200647 doi (DE-627)DOAJ042757517 (DE-599)DOAJ029fae73139846f48c5278a2b5f406d1 DE-627 ger DE-627 rakwb eng Yi Tian verfasserin aut Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics. batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q Haifeng Hu verfasserin aut Peipei Chen verfasserin aut Fengliang Dong verfasserin aut Hui Huang verfasserin aut Lihua Xu verfasserin aut Lanqin Yan verfasserin aut Zhiwei Song verfasserin aut Taoran Xu verfasserin aut Weiguo Chu verfasserin aut In Advanced Science Wiley, 2015 9(2022), 15, Seite n/a-n/a (DE-627)817357777 (DE-600)2808093-2 21983844 nnns volume:9 year:2022 number:15 pages:n/a-n/a https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 kostenfrei https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/toc/2198-3844 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 9 2022 15 n/a-n/a
spelling	10.1002/advs.202200647 doi (DE-627)DOAJ042757517 (DE-599)DOAJ029fae73139846f48c5278a2b5f406d1 DE-627 ger DE-627 rakwb eng Yi Tian verfasserin aut Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics. batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q Haifeng Hu verfasserin aut Peipei Chen verfasserin aut Fengliang Dong verfasserin aut Hui Huang verfasserin aut Lihua Xu verfasserin aut Lanqin Yan verfasserin aut Zhiwei Song verfasserin aut Taoran Xu verfasserin aut Weiguo Chu verfasserin aut In Advanced Science Wiley, 2015 9(2022), 15, Seite n/a-n/a (DE-627)817357777 (DE-600)2808093-2 21983844 nnns volume:9 year:2022 number:15 pages:n/a-n/a https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 kostenfrei https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/toc/2198-3844 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 9 2022 15 n/a-n/a
allfields_unstemmed	10.1002/advs.202200647 doi (DE-627)DOAJ042757517 (DE-599)DOAJ029fae73139846f48c5278a2b5f406d1 DE-627 ger DE-627 rakwb eng Yi Tian verfasserin aut Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics. batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q Haifeng Hu verfasserin aut Peipei Chen verfasserin aut Fengliang Dong verfasserin aut Hui Huang verfasserin aut Lihua Xu verfasserin aut Lanqin Yan verfasserin aut Zhiwei Song verfasserin aut Taoran Xu verfasserin aut Weiguo Chu verfasserin aut In Advanced Science Wiley, 2015 9(2022), 15, Seite n/a-n/a (DE-627)817357777 (DE-600)2808093-2 21983844 nnns volume:9 year:2022 number:15 pages:n/a-n/a https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 kostenfrei https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/toc/2198-3844 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 9 2022 15 n/a-n/a
allfieldsGer	10.1002/advs.202200647 doi (DE-627)DOAJ042757517 (DE-599)DOAJ029fae73139846f48c5278a2b5f406d1 DE-627 ger DE-627 rakwb eng Yi Tian verfasserin aut Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics. batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q Haifeng Hu verfasserin aut Peipei Chen verfasserin aut Fengliang Dong verfasserin aut Hui Huang verfasserin aut Lihua Xu verfasserin aut Lanqin Yan verfasserin aut Zhiwei Song verfasserin aut Taoran Xu verfasserin aut Weiguo Chu verfasserin aut In Advanced Science Wiley, 2015 9(2022), 15, Seite n/a-n/a (DE-627)817357777 (DE-600)2808093-2 21983844 nnns volume:9 year:2022 number:15 pages:n/a-n/a https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 kostenfrei https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/toc/2198-3844 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 9 2022 15 n/a-n/a
allfieldsSound	10.1002/advs.202200647 doi (DE-627)DOAJ042757517 (DE-599)DOAJ029fae73139846f48c5278a2b5f406d1 DE-627 ger DE-627 rakwb eng Yi Tian verfasserin aut Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics. batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q Haifeng Hu verfasserin aut Peipei Chen verfasserin aut Fengliang Dong verfasserin aut Hui Huang verfasserin aut Lihua Xu verfasserin aut Lanqin Yan verfasserin aut Zhiwei Song verfasserin aut Taoran Xu verfasserin aut Weiguo Chu verfasserin aut In Advanced Science Wiley, 2015 9(2022), 15, Seite n/a-n/a (DE-627)817357777 (DE-600)2808093-2 21983844 nnns volume:9 year:2022 number:15 pages:n/a-n/a https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 kostenfrei https://doi.org/10.1002/advs.202200647 kostenfrei https://doaj.org/toc/2198-3844 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 9 2022 15 n/a-n/a
language	English
source	In Advanced Science 9(2022), 15, Seite n/a-n/a volume:9 year:2022 number:15 pages:n/a-n/a
sourceStr	In Advanced Science 9(2022), 15, Seite n/a-n/a volume:9 year:2022 number:15 pages:n/a-n/a
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection Science Q
isfreeaccess_bool	true
container_title	Advanced Science
authorswithroles_txt_mv	Yi Tian @@aut@@ Haifeng Hu @@aut@@ Peipei Chen @@aut@@ Fengliang Dong @@aut@@ Hui Huang @@aut@@ Lihua Xu @@aut@@ Lanqin Yan @@aut@@ Zhiwei Song @@aut@@ Taoran Xu @@aut@@ Weiguo Chu @@aut@@
publishDateDaySort_date	2022-01-01T00:00:00Z
hierarchy_top_id	817357777
id	DOAJ042757517
language_de	englisch
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author	Yi Tian
spellingShingle	Yi Tian misc batch fabrication misc dielectric walls/layers misc localized surface plasmon resonance (LSPR) misc SERS chip design misc surface plasmon polariton (SPP) misc trace detection misc Science misc Q Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications
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topic_title	Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications batch fabrication dielectric walls/layers localized surface plasmon resonance (LSPR) SERS chip design surface plasmon polariton (SPP) trace detection
topic	misc batch fabrication misc dielectric walls/layers misc localized surface plasmon resonance (LSPR) misc SERS chip design misc surface plasmon polariton (SPP) misc trace detection misc Science misc Q
topic_unstemmed	misc batch fabrication misc dielectric walls/layers misc localized surface plasmon resonance (LSPR) misc SERS chip design misc surface plasmon polariton (SPP) misc trace detection misc Science misc Q
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title	Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications
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title_full	Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications
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author_browse	Yi Tian Haifeng Hu Peipei Chen Fengliang Dong Hui Huang Lihua Xu Lanqin Yan Zhiwei Song Taoran Xu Weiguo Chu
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title_sort	dielectric walls/layers modulated 3d periodically structured sers chips: design, batch fabrication, and applications
title_auth	Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications
abstract	Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.
abstractGer	Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.
abstract_unstemmed	Abstract As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low‐cost batch‐fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.
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title_short	Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications
url	https://doi.org/10.1002/advs.202200647 https://doaj.org/article/029fae73139846f48c5278a2b5f406d1 https://doaj.org/toc/2198-3844
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up_date	2024-07-03T13:52:21.291Z
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Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half‐SPPplasmonic material‐dielectric‐wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO2 based SERS chips show an enhancement factor of 8.9 × 1010, 265 times higher relative to the chips with far thinner SiO2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost‐effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. 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