Area Reduction of Combinational Circuits Considering Path Sensitization

Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysi...
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Autor*in:	S. Abolmaali [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	area reduction gate resizing path sensitization timing analysis viability analysis.

Übergeordnetes Werk:	In: Iranian Journal of Electrical and Electronic Engineering - Iran University of Science and Technology, 2018, 17(2021), 3, Seite 1730-1730
Übergeordnetes Werk:	volume:17 ; year:2021 ; number:3 ; pages:1730-1730

Links:	Link aufrufen Link aufrufen Journal toc Journal toc

Katalog-ID:	DOAJ056265395

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520			\|a Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
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spelling	(DE-627)DOAJ056265395 (DE-599)DOAJffff1199471049f682577a5232af6aee DE-627 ger DE-627 rakwb eng TK1-9971 S. Abolmaali verfasserin aut Area Reduction of Combinational Circuits Considering Path Sensitization 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method. area reduction gate resizing path sensitization timing analysis viability analysis. Electrical engineering. Electronics. Nuclear engineering In Iranian Journal of Electrical and Electronic Engineering Iran University of Science and Technology, 2018 17(2021), 3, Seite 1730-1730 (DE-627)1031245618 23833890 nnns volume:17 year:2021 number:3 pages:1730-1730 https://doaj.org/article/ffff1199471049f682577a5232af6aee kostenfrei http://ijeee.iust.ac.ir/article-1-1730-en.html kostenfrei https://doaj.org/toc/1735-2827 Journal toc kostenfrei https://doaj.org/toc/2383-3890 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ SSG-OLC-PHA GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 17 2021 3 1730-1730
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allfieldsGer	(DE-627)DOAJ056265395 (DE-599)DOAJffff1199471049f682577a5232af6aee DE-627 ger DE-627 rakwb eng TK1-9971 S. Abolmaali verfasserin aut Area Reduction of Combinational Circuits Considering Path Sensitization 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method. area reduction gate resizing path sensitization timing analysis viability analysis. Electrical engineering. Electronics. Nuclear engineering In Iranian Journal of Electrical and Electronic Engineering Iran University of Science and Technology, 2018 17(2021), 3, Seite 1730-1730 (DE-627)1031245618 23833890 nnns volume:17 year:2021 number:3 pages:1730-1730 https://doaj.org/article/ffff1199471049f682577a5232af6aee kostenfrei http://ijeee.iust.ac.ir/article-1-1730-en.html kostenfrei https://doaj.org/toc/1735-2827 Journal toc kostenfrei https://doaj.org/toc/2383-3890 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ SSG-OLC-PHA GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 17 2021 3 1730-1730
allfieldsSound	(DE-627)DOAJ056265395 (DE-599)DOAJffff1199471049f682577a5232af6aee DE-627 ger DE-627 rakwb eng TK1-9971 S. Abolmaali verfasserin aut Area Reduction of Combinational Circuits Considering Path Sensitization 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method. area reduction gate resizing path sensitization timing analysis viability analysis. Electrical engineering. Electronics. Nuclear engineering In Iranian Journal of Electrical and Electronic Engineering Iran University of Science and Technology, 2018 17(2021), 3, Seite 1730-1730 (DE-627)1031245618 23833890 nnns volume:17 year:2021 number:3 pages:1730-1730 https://doaj.org/article/ffff1199471049f682577a5232af6aee kostenfrei http://ijeee.iust.ac.ir/article-1-1730-en.html kostenfrei https://doaj.org/toc/1735-2827 Journal toc kostenfrei https://doaj.org/toc/2383-3890 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ SSG-OLC-PHA GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 17 2021 3 1730-1730
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callnumber-first	T - Technology
author	S. Abolmaali
spellingShingle	S. Abolmaali misc TK1-9971 misc area reduction misc gate resizing misc path sensitization misc timing analysis misc viability analysis. misc Electrical engineering. Electronics. Nuclear engineering Area Reduction of Combinational Circuits Considering Path Sensitization
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topic_title	TK1-9971 Area Reduction of Combinational Circuits Considering Path Sensitization area reduction gate resizing path sensitization timing analysis viability analysis
topic	misc TK1-9971 misc area reduction misc gate resizing misc path sensitization misc timing analysis misc viability analysis. misc Electrical engineering. Electronics. Nuclear engineering
topic_unstemmed	misc TK1-9971 misc area reduction misc gate resizing misc path sensitization misc timing analysis misc viability analysis. misc Electrical engineering. Electronics. Nuclear engineering
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title	Area Reduction of Combinational Circuits Considering Path Sensitization
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title_full	Area Reduction of Combinational Circuits Considering Path Sensitization
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title_sort	area reduction of combinational circuits considering path sensitization
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title_auth	Area Reduction of Combinational Circuits Considering Path Sensitization
abstract	Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
abstractGer	Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
abstract_unstemmed	Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
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