Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies. Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Ruben Nieto [verfasserIn] Raul Mateos [verfasserIn] Alvaro Hernandez [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2020

Schlagwörter:	Power-line communication channel equalizer channel estimation multiprocessor system-on-chip

Übergeordnetes Werk:	In: IEEE Access - IEEE, 2014, 8(2020), Seite 188552-188563
Übergeordnetes Werk:	volume:8 ; year:2020 ; pages:188552-188563

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.1109/ACCESS.2020.3031476

Katalog-ID:	DOAJ056292856

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allfieldsSound	10.1109/ACCESS.2020.3031476 doi (DE-627)DOAJ056292856 (DE-599)DOAJ5b77dd3796e14e3c9a65ae6be9dfdbc1 DE-627 ger DE-627 rakwb eng TK1-9971 Ruben Nieto verfasserin aut Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies. Power-line communication channel equalizer channel estimation multiprocessor system-on-chip Electrical engineering. Electronics. Nuclear engineering Raul Mateos verfasserin aut Alvaro Hernandez verfasserin aut In IEEE Access IEEE, 2014 8(2020), Seite 188552-188563 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:8 year:2020 pages:188552-188563 https://doi.org/10.1109/ACCESS.2020.3031476 kostenfrei https://doaj.org/article/5b77dd3796e14e3c9a65ae6be9dfdbc1 kostenfrei https://ieeexplore.ieee.org/document/9225136/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 8 2020 188552-188563
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callnumber-first	T - Technology
author	Ruben Nieto
spellingShingle	Ruben Nieto misc TK1-9971 misc Power-line communication misc channel equalizer misc channel estimation misc multiprocessor system-on-chip misc Electrical engineering. Electronics. Nuclear engineering Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
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topic_title	TK1-9971 Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution Power-line communication channel equalizer channel estimation multiprocessor system-on-chip
topic	misc TK1-9971 misc Power-line communication misc channel equalizer misc channel estimation misc multiprocessor system-on-chip misc Electrical engineering. Electronics. Nuclear engineering
topic_unstemmed	misc TK1-9971 misc Power-line communication misc channel equalizer misc channel estimation misc multiprocessor system-on-chip misc Electrical engineering. Electronics. Nuclear engineering
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title	Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
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title_full	Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
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title_sort	performance improvement of plc channel estimator and ascet equalizer in a fbmc transmultiplexer based on a multi-core solution
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title_auth	Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
abstract	Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.
abstractGer	Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.
abstract_unstemmed	Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.
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title_short	Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
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Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power-line communication</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">channel equalizer</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">channel estimation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">multiprocessor system-on-chip</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electrical engineering. Electronics. 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