VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation

The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in t...
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Autor*in:	Wen-Ho Juang [verfasserIn] Shin-Chi Lai [verfasserIn] Ching-Hsing Luo [verfasserIn] Shuenn-Yuh Lee [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2018

Schlagwörter:	Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT

Übergeordnetes Werk:	In: IEEE Access - IEEE, 2014, 6(2018), Seite 30491-30500
Übergeordnetes Werk:	volume:6 ; year:2018 ; pages:30491-30500

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.1109/ACCESS.2018.2833623

Katalog-ID:	DOAJ056390025

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520			\|a The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications.
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allfields	10.1109/ACCESS.2018.2833623 doi (DE-627)DOAJ056390025 (DE-599)DOAJc8daab7e8a92406b931920720eb08fbc DE-627 ger DE-627 rakwb eng TK1-9971 Wen-Ho Juang verfasserin aut VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications. Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering Shin-Chi Lai verfasserin aut Ching-Hsing Luo verfasserin aut Shuenn-Yuh Lee verfasserin aut In IEEE Access IEEE, 2014 6(2018), Seite 30491-30500 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:6 year:2018 pages:30491-30500 https://doi.org/10.1109/ACCESS.2018.2833623 kostenfrei https://doaj.org/article/c8daab7e8a92406b931920720eb08fbc kostenfrei https://ieeexplore.ieee.org/document/8355523/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 6 2018 30491-30500
spelling	10.1109/ACCESS.2018.2833623 doi (DE-627)DOAJ056390025 (DE-599)DOAJc8daab7e8a92406b931920720eb08fbc DE-627 ger DE-627 rakwb eng TK1-9971 Wen-Ho Juang verfasserin aut VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications. Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering Shin-Chi Lai verfasserin aut Ching-Hsing Luo verfasserin aut Shuenn-Yuh Lee verfasserin aut In IEEE Access IEEE, 2014 6(2018), Seite 30491-30500 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:6 year:2018 pages:30491-30500 https://doi.org/10.1109/ACCESS.2018.2833623 kostenfrei https://doaj.org/article/c8daab7e8a92406b931920720eb08fbc kostenfrei https://ieeexplore.ieee.org/document/8355523/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 6 2018 30491-30500
allfields_unstemmed	10.1109/ACCESS.2018.2833623 doi (DE-627)DOAJ056390025 (DE-599)DOAJc8daab7e8a92406b931920720eb08fbc DE-627 ger DE-627 rakwb eng TK1-9971 Wen-Ho Juang verfasserin aut VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications. Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering Shin-Chi Lai verfasserin aut Ching-Hsing Luo verfasserin aut Shuenn-Yuh Lee verfasserin aut In IEEE Access IEEE, 2014 6(2018), Seite 30491-30500 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:6 year:2018 pages:30491-30500 https://doi.org/10.1109/ACCESS.2018.2833623 kostenfrei https://doaj.org/article/c8daab7e8a92406b931920720eb08fbc kostenfrei https://ieeexplore.ieee.org/document/8355523/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 6 2018 30491-30500
allfieldsGer	10.1109/ACCESS.2018.2833623 doi (DE-627)DOAJ056390025 (DE-599)DOAJc8daab7e8a92406b931920720eb08fbc DE-627 ger DE-627 rakwb eng TK1-9971 Wen-Ho Juang verfasserin aut VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications. Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering Shin-Chi Lai verfasserin aut Ching-Hsing Luo verfasserin aut Shuenn-Yuh Lee verfasserin aut In IEEE Access IEEE, 2014 6(2018), Seite 30491-30500 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:6 year:2018 pages:30491-30500 https://doi.org/10.1109/ACCESS.2018.2833623 kostenfrei https://doaj.org/article/c8daab7e8a92406b931920720eb08fbc kostenfrei https://ieeexplore.ieee.org/document/8355523/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 6 2018 30491-30500
allfieldsSound	10.1109/ACCESS.2018.2833623 doi (DE-627)DOAJ056390025 (DE-599)DOAJc8daab7e8a92406b931920720eb08fbc DE-627 ger DE-627 rakwb eng TK1-9971 Wen-Ho Juang verfasserin aut VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications. Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering Shin-Chi Lai verfasserin aut Ching-Hsing Luo verfasserin aut Shuenn-Yuh Lee verfasserin aut In IEEE Access IEEE, 2014 6(2018), Seite 30491-30500 (DE-627)728440385 (DE-600)2687964-5 21693536 nnns volume:6 year:2018 pages:30491-30500 https://doi.org/10.1109/ACCESS.2018.2833623 kostenfrei https://doaj.org/article/c8daab7e8a92406b931920720eb08fbc kostenfrei https://ieeexplore.ieee.org/document/8355523/ kostenfrei https://doaj.org/toc/2169-3536 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 6 2018 30491-30500
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topic_facet	Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT Electrical engineering. Electronics. Nuclear engineering
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authorswithroles_txt_mv	Wen-Ho Juang @@aut@@ Shin-Chi Lai @@aut@@ Ching-Hsing Luo @@aut@@ Shuenn-Yuh Lee @@aut@@
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callnumber-first	T - Technology
author	Wen-Ho Juang
spellingShingle	Wen-Ho Juang misc TK1-9971 misc Hopping discrete Fourier transform (HDFT) misc sliding discrete Fourier transform (SDFT) misc recursive discrete Fourier transform (RDFT) misc recursive DFT-based UVT misc Electrical engineering. Electronics. Nuclear engineering VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
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topic_title	TK1-9971 VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation Hopping discrete Fourier transform (HDFT) sliding discrete Fourier transform (SDFT) recursive discrete Fourier transform (RDFT) recursive DFT-based UVT
topic	misc TK1-9971 misc Hopping discrete Fourier transform (HDFT) misc sliding discrete Fourier transform (SDFT) misc recursive discrete Fourier transform (RDFT) misc recursive DFT-based UVT misc Electrical engineering. Electronics. Nuclear engineering
topic_unstemmed	misc TK1-9971 misc Hopping discrete Fourier transform (HDFT) misc sliding discrete Fourier transform (SDFT) misc recursive discrete Fourier transform (RDFT) misc recursive DFT-based UVT misc Electrical engineering. Electronics. Nuclear engineering
topic_browse	misc TK1-9971 misc Hopping discrete Fourier transform (HDFT) misc sliding discrete Fourier transform (SDFT) misc recursive discrete Fourier transform (RDFT) misc recursive DFT-based UVT misc Electrical engineering. Electronics. Nuclear engineering
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title	VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
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title_full	VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
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title_sort	vlsi architecture for novel hopping discrete fourier transform computation
callnumber	TK1-9971
title_auth	VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
abstract	The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications.
abstractGer	The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications.
abstract_unstemmed	The hopping discrete Fourier transform (HDFT) is a new method applied for time-frequency spectral analysis of time-varying signals. In the implementation of HDFT algorithms, the updating vector transform (UVT) plays a key role, and therefore a novel recursive DFT-based UVT formula is introduced in the proposed design for a HDFT algorithm and its architecture. The perceived advantages can be summarized as: 1) the proposed algorithm reduces the number of multiplications, additions, and coefficients by 42.3%, 33.3%, and 50%, respectively, compared with Park's method under the settings of an M-sample complex input sequence (M = 256), and an N-point recursive DFT computation scheme (N = 64) for time hop L (L = 4); 2) by adopting the hardware-sharing scheme and the register-shifting concept, the proposed design only takes nine multipliers and 12 adders for realization. The proposed hardware accelerator can be implemented using a field-programmable gate array, which can operate at 48.33 MHz clock rate. The resource utilization of combinational logic lookup tables (LUTs) and digital signal processing (DSP) blocks reduced by 11.7% and 42.5% compared with Juang et al.'s work. For very-large-scale integration realizations, the proposed design would be more powerful than other existing algorithms in future applications focusing on DSP, filtering, and communications.
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title_short	VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
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VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation

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