Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy

A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturin...
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Gespeichert in:

Autor*in:	ZAGAN, I. [verfasserIn] GAITAN, V. G. [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2016

Schlagwörter:	field programmable gate arrays pipeline processing architecture scheduling operating systems

Übergeordnetes Werk:	In: Advances in Electrical and Computer Engineering - Stefan cel Mare University of Suceava, 2010, 16(2016), 4, Seite 45-50
Übergeordnetes Werk:	volume:16 ; year:2016 ; number:4 ; pages:45-50

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc Journal toc

DOI / URN:	10.4316/AECE.2016.04007

Katalog-ID:	DOAJ070947880

Internformat


LEADER	01000caa a22002652 4500
001	DOAJ070947880
003	DE-627
005	20230309095145.0
007	cr uuu---uuuuu
008	230228s2016 xx \|\|\|\|\|o 00\| \|\|eng c
024	7		\|a 10.4316/AECE.2016.04007 \|2 doi
035			\|a (DE-627)DOAJ070947880
035			\|a (DE-599)DOAJe1b372c21783496598f0ad2b761a3492
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
041			\|a eng
050		0	\|a TK1-9971
050		0	\|a TK7885-7895
100	0		\|a ZAGAN, I. \|e verfasserin \|4 aut
245	1	0	\|a Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
264		1	\|c 2016
336			\|a Text \|b txt \|2 rdacontent
337			\|a Computermedien \|b c \|2 rdamedia
338			\|a Online-Ressource \|b cr \|2 rdacarrier
520			\|a A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
650		4	\|a field programmable gate arrays
650		4	\|a pipeline processing
650		4	\|a architecture
650		4	\|a scheduling
650		4	\|a operating systems
653		0	\|a Electrical engineering. Electronics. Nuclear engineering
653		0	\|a Computer engineering. Computer hardware
700	0		\|a GAITAN, V. G. \|e verfasserin \|4 aut
773	0	8	\|i In \|t Advances in Electrical and Computer Engineering \|d Stefan cel Mare University of Suceava, 2010 \|g 16(2016), 4, Seite 45-50 \|w (DE-627)625422015 \|w (DE-600)2551047-2 \|x 18447600 \|7 nnns
773	1	8	\|g volume:16 \|g year:2016 \|g number:4 \|g pages:45-50
856	4	0	\|u https://doi.org/10.4316/AECE.2016.04007 \|z kostenfrei
856	4	0	\|u https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 \|z kostenfrei
856	4	0	\|u http://dx.doi.org/10.4316/AECE.2016.04007 \|z kostenfrei
856	4	2	\|u https://doaj.org/toc/1582-7445 \|y Journal toc \|z kostenfrei
856	4	2	\|u https://doaj.org/toc/1844-7600 \|y Journal toc \|z kostenfrei
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_DOAJ
912			\|a GBV_ILN_11
912			\|a GBV_ILN_20
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_39
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_63
912			\|a GBV_ILN_65
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_95
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_151
912			\|a GBV_ILN_161
912			\|a GBV_ILN_170
912			\|a GBV_ILN_213
912			\|a GBV_ILN_230
912			\|a GBV_ILN_285
912			\|a GBV_ILN_293
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_4012
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4126
912			\|a GBV_ILN_4249
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4325
912			\|a GBV_ILN_4326
912			\|a GBV_ILN_4335
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4367
912			\|a GBV_ILN_4700
951			\|a AR
952			\|d 16 \|j 2016 \|e 4 \|h 45-50

Indexfelder

author_variant	i z iz v g g vg vgg
matchkey_str	article:18447600:2016----::mrvnteefracsfhnparcsouigcsoitruta
hierarchy_sort_str	2016
callnumber-subject-code	TK
publishDate	2016
allfields	10.4316/AECE.2016.04007 doi (DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492 DE-627 ger DE-627 rakwb eng TK1-9971 TK7885-7895 ZAGAN, I. verfasserin aut Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy 2016 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained. field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware GAITAN, V. G. verfasserin aut In Advances in Electrical and Computer Engineering Stefan cel Mare University of Suceava, 2010 16(2016), 4, Seite 45-50 (DE-627)625422015 (DE-600)2551047-2 18447600 nnns volume:16 year:2016 number:4 pages:45-50 https://doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 kostenfrei http://dx.doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/toc/1582-7445 Journal toc kostenfrei https://doaj.org/toc/1844-7600 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 16 2016 4 45-50
spelling	10.4316/AECE.2016.04007 doi (DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492 DE-627 ger DE-627 rakwb eng TK1-9971 TK7885-7895 ZAGAN, I. verfasserin aut Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy 2016 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained. field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware GAITAN, V. G. verfasserin aut In Advances in Electrical and Computer Engineering Stefan cel Mare University of Suceava, 2010 16(2016), 4, Seite 45-50 (DE-627)625422015 (DE-600)2551047-2 18447600 nnns volume:16 year:2016 number:4 pages:45-50 https://doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 kostenfrei http://dx.doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/toc/1582-7445 Journal toc kostenfrei https://doaj.org/toc/1844-7600 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 16 2016 4 45-50
allfields_unstemmed	10.4316/AECE.2016.04007 doi (DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492 DE-627 ger DE-627 rakwb eng TK1-9971 TK7885-7895 ZAGAN, I. verfasserin aut Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy 2016 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained. field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware GAITAN, V. G. verfasserin aut In Advances in Electrical and Computer Engineering Stefan cel Mare University of Suceava, 2010 16(2016), 4, Seite 45-50 (DE-627)625422015 (DE-600)2551047-2 18447600 nnns volume:16 year:2016 number:4 pages:45-50 https://doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 kostenfrei http://dx.doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/toc/1582-7445 Journal toc kostenfrei https://doaj.org/toc/1844-7600 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 16 2016 4 45-50
allfieldsGer	10.4316/AECE.2016.04007 doi (DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492 DE-627 ger DE-627 rakwb eng TK1-9971 TK7885-7895 ZAGAN, I. verfasserin aut Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy 2016 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained. field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware GAITAN, V. G. verfasserin aut In Advances in Electrical and Computer Engineering Stefan cel Mare University of Suceava, 2010 16(2016), 4, Seite 45-50 (DE-627)625422015 (DE-600)2551047-2 18447600 nnns volume:16 year:2016 number:4 pages:45-50 https://doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 kostenfrei http://dx.doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/toc/1582-7445 Journal toc kostenfrei https://doaj.org/toc/1844-7600 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 16 2016 4 45-50
allfieldsSound	10.4316/AECE.2016.04007 doi (DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492 DE-627 ger DE-627 rakwb eng TK1-9971 TK7885-7895 ZAGAN, I. verfasserin aut Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy 2016 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained. field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware GAITAN, V. G. verfasserin aut In Advances in Electrical and Computer Engineering Stefan cel Mare University of Suceava, 2010 16(2016), 4, Seite 45-50 (DE-627)625422015 (DE-600)2551047-2 18447600 nnns volume:16 year:2016 number:4 pages:45-50 https://doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 kostenfrei http://dx.doi.org/10.4316/AECE.2016.04007 kostenfrei https://doaj.org/toc/1582-7445 Journal toc kostenfrei https://doaj.org/toc/1844-7600 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 16 2016 4 45-50
language	English
source	In Advances in Electrical and Computer Engineering 16(2016), 4, Seite 45-50 volume:16 year:2016 number:4 pages:45-50
sourceStr	In Advances in Electrical and Computer Engineering 16(2016), 4, Seite 45-50 volume:16 year:2016 number:4 pages:45-50
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	field programmable gate arrays pipeline processing architecture scheduling operating systems Electrical engineering. Electronics. Nuclear engineering Computer engineering. Computer hardware
isfreeaccess_bool	true
container_title	Advances in Electrical and Computer Engineering
authorswithroles_txt_mv	ZAGAN, I. @@aut@@ GAITAN, V. G. @@aut@@
publishDateDaySort_date	2016-01-01T00:00:00Z
hierarchy_top_id	625422015
id	DOAJ070947880
language_de	englisch
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ070947880</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230309095145.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">230228s2016 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.4316/AECE.2016.04007</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ070947880</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJe1b372c21783496598f0ad2b761a3492</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK1-9971</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7885-7895</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">ZAGAN, I.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">field programmable gate arrays</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">pipeline processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">scheduling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">operating systems</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electrical engineering. Electronics. Nuclear engineering</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Computer engineering. Computer hardware</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">GAITAN, V. G.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Advances in Electrical and Computer Engineering</subfield><subfield code="d">Stefan cel Mare University of Suceava, 2010</subfield><subfield code="g">16(2016), 4, Seite 45-50</subfield><subfield code="w">(DE-627)625422015</subfield><subfield code="w">(DE-600)2551047-2</subfield><subfield code="x">18447600</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:16</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:4</subfield><subfield code="g">pages:45-50</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.4316/AECE.2016.04007</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/e1b372c21783496598f0ad2b761a3492</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://dx.doi.org/10.4316/AECE.2016.04007</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1582-7445</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1844-7600</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4367</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">16</subfield><subfield code="j">2016</subfield><subfield code="e">4</subfield><subfield code="h">45-50</subfield></datafield></record></collection>
callnumber-first	T - Technology
author	ZAGAN, I.
spellingShingle	ZAGAN, I. misc TK1-9971 misc TK7885-7895 misc field programmable gate arrays misc pipeline processing misc architecture misc scheduling misc operating systems misc Electrical engineering. Electronics. Nuclear engineering misc Computer engineering. Computer hardware Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
authorStr	ZAGAN, I.
ppnlink_with_tag_str_mv	@@773@@(DE-627)625422015
format	electronic Article
delete_txt_mv	keep
author_role	aut aut
collection	DOAJ
remote_str	true
callnumber-label	TK1-9971
illustrated	Not Illustrated
issn	18447600
topic_title	TK1-9971 TK7885-7895 Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy field programmable gate arrays pipeline processing architecture scheduling operating systems
topic	misc TK1-9971 misc TK7885-7895 misc field programmable gate arrays misc pipeline processing misc architecture misc scheduling misc operating systems misc Electrical engineering. Electronics. Nuclear engineering misc Computer engineering. Computer hardware
topic_unstemmed	misc TK1-9971 misc TK7885-7895 misc field programmable gate arrays misc pipeline processing misc architecture misc scheduling misc operating systems misc Electrical engineering. Electronics. Nuclear engineering misc Computer engineering. Computer hardware
topic_browse	misc TK1-9971 misc TK7885-7895 misc field programmable gate arrays misc pipeline processing misc architecture misc scheduling misc operating systems misc Electrical engineering. Electronics. Nuclear engineering misc Computer engineering. Computer hardware
format_facet	Elektronische Aufsätze Aufsätze Elektronische Ressource
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	cr
hierarchy_parent_title	Advances in Electrical and Computer Engineering
hierarchy_parent_id	625422015
hierarchy_top_title	Advances in Electrical and Computer Engineering
isfreeaccess_txt	true
familylinks_str_mv	(DE-627)625422015 (DE-600)2551047-2
title	Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
ctrlnum	(DE-627)DOAJ070947880 (DE-599)DOAJe1b372c21783496598f0ad2b761a3492
title_full	Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
author_sort	ZAGAN, I.
journal	Advances in Electrical and Computer Engineering
journalStr	Advances in Electrical and Computer Engineering
callnumber-first-code	T
lang_code	eng
isOA_bool	true
recordtype	marc
publishDateSort	2016
contenttype_str_mv	txt
container_start_page	45
author_browse	ZAGAN, I. GAITAN, V. G.
container_volume	16
class	TK1-9971 TK7885-7895
format_se	Elektronische Aufsätze
author-letter	ZAGAN, I.
doi_str_mv	10.4316/AECE.2016.04007
author2-role	verfasserin
title_sort	improving the performances of the nmpra processor using a custom interrupt management scheduling policy
callnumber	TK1-9971
title_auth	Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
abstract	A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
abstractGer	A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
abstract_unstemmed	A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700
container_issue	4
title_short	Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
url	https://doi.org/10.4316/AECE.2016.04007 https://doaj.org/article/e1b372c21783496598f0ad2b761a3492 http://dx.doi.org/10.4316/AECE.2016.04007 https://doaj.org/toc/1582-7445 https://doaj.org/toc/1844-7600
remote_bool	true
author2	GAITAN, V. G.
author2Str	GAITAN, V. G.
ppnlink	625422015
callnumber-subject	TK - Electrical and Nuclear Engineering
mediatype_str_mv	c
isOA_txt	true
hochschulschrift_bool	false
doi_str	10.4316/AECE.2016.04007
callnumber-a	TK1-9971
up_date	2024-07-03T17:36:07.496Z
_version_	1803580255762382848
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ070947880</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230309095145.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">230228s2016 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.4316/AECE.2016.04007</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ070947880</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJe1b372c21783496598f0ad2b761a3492</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK1-9971</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7885-7895</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">ZAGAN, I.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">field programmable gate arrays</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">pipeline processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">scheduling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">operating systems</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electrical engineering. Electronics. Nuclear engineering</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Computer engineering. Computer hardware</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">GAITAN, V. G.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Advances in Electrical and Computer Engineering</subfield><subfield code="d">Stefan cel Mare University of Suceava, 2010</subfield><subfield code="g">16(2016), 4, Seite 45-50</subfield><subfield code="w">(DE-627)625422015</subfield><subfield code="w">(DE-600)2551047-2</subfield><subfield code="x">18447600</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:16</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:4</subfield><subfield code="g">pages:45-50</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.4316/AECE.2016.04007</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/e1b372c21783496598f0ad2b761a3492</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://dx.doi.org/10.4316/AECE.2016.04007</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1582-7445</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1844-7600</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4367</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">16</subfield><subfield code="j">2016</subfield><subfield code="e">4</subfield><subfield code="h">45-50</subfield></datafield></record></collection>
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Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy

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