Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM

Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8<sup<+&...
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Autor*in:	Soonbum Song [verfasserIn] Youngmin Kim [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2022

Schlagwörter:	von Neumann bottleneck memory wall SRAM in-memory computing (IMC) Process-in-Memory (PIM)

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 11(2022), 6, p 929
Übergeordnetes Werk:	volume:11 ; year:2022 ; number:6, p 929

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics11060929

Katalog-ID:	DOAJ084617837

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language	English
source	In Electronics 11(2022), 6, p 929 volume:11 year:2022 number:6, p 929
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institution	findex.gbv.de
topic_facet	von Neumann bottleneck memory wall SRAM in-memory computing (IMC) Process-in-Memory (PIM) Electronics
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container_title	Electronics
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callnumber-first	T - Technology
author	Soonbum Song
spellingShingle	Soonbum Song misc TK7800-8360 misc von Neumann bottleneck misc memory wall misc SRAM misc in-memory computing (IMC) misc Process-in-Memory (PIM) misc Electronics Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM
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topic_title	TK7800-8360 Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM von Neumann bottleneck memory wall SRAM in-memory computing (IMC) Process-in-Memory (PIM)
topic	misc TK7800-8360 misc von Neumann bottleneck misc memory wall misc SRAM misc in-memory computing (IMC) misc Process-in-Memory (PIM) misc Electronics
topic_unstemmed	misc TK7800-8360 misc von Neumann bottleneck misc memory wall misc SRAM misc in-memory computing (IMC) misc Process-in-Memory (PIM) misc Electronics
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title	Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM
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title_full	Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM
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title_sort	novel in-memory computing adder using 8<sup<+</sup<t sram
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title_auth	Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM
abstract	Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8<sup<+</sup<T SRAM IMC circuit based on 8<sup<+</sup<T differential SRAM (8<sup<+</sup<T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8<sup<+</sup<T SRAM-based IMC approximate adder, which are based on the 8<sup<+</sup<T SRAM IMC circuit. The 8<sup<+</sup<T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8<sup<+</sup<T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8<sup<+</sup<T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8<sup<+</sup<T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.
abstractGer	Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8<sup<+</sup<T SRAM IMC circuit based on 8<sup<+</sup<T differential SRAM (8<sup<+</sup<T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8<sup<+</sup<T SRAM-based IMC approximate adder, which are based on the 8<sup<+</sup<T SRAM IMC circuit. The 8<sup<+</sup<T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8<sup<+</sup<T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8<sup<+</sup<T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8<sup<+</sup<T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.
abstract_unstemmed	Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8<sup<+</sup<T SRAM IMC circuit based on 8<sup<+</sup<T differential SRAM (8<sup<+</sup<T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8<sup<+</sup<T SRAM-based IMC approximate adder, which are based on the 8<sup<+</sup<T SRAM IMC circuit. The 8<sup<+</sup<T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8<sup<+</sup<T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8<sup<+</sup<T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8<sup<+</sup<T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.
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title_short	Novel In-Memory Computing Adder Using 8<sup<+</sup<T SRAM
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