Design and Implementation of a Configurable Real-Time FPGA-Based Geometric Symmetry-CFAR Processer for Radar Target Detection
A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar...
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Gespeichert in:
| Autor*in: |
Waleed Khalid [verfasserIn] Mohammed Hussein Ali [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Arabisch ; Englisch |
| Erschienen: |
2011 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
In: Journal of Engineering and Sustainable Development - Mustansiriyah University/College of Engineering, 2019, 15(2011), 3 |
|---|---|
| Übergeordnetes Werk: |
volume:15 ; year:2011 ; number:3 |
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| 520 | |a A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. | ||
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(DE-627)DOAJ086478621 (DE-599)DOAJ193d2a2c67a6470986cb28ab3de3da88 DE-627 ger DE-627 rakwb ara eng TA1-2040 Waleed Khalid verfasserin aut Design and Implementation of a Configurable Real-Time FPGA-Based Geometric Symmetry-CFAR Processer for Radar Target Detection 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. FPGA constant false alarm rate radar target detection CFAR processer Engineering (General). Civil engineering (General) Mohammed Hussein Ali verfasserin aut In Journal of Engineering and Sustainable Development Mustansiriyah University/College of Engineering, 2019 15(2011), 3 (DE-627)1688152911 25200925 nnns volume:15 year:2011 number:3 https://doaj.org/article/193d2a2c67a6470986cb28ab3de3da88 kostenfrei https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1331 kostenfrei https://doaj.org/toc/2520-0917 Journal toc kostenfrei https://doaj.org/toc/2520-0925 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ AR 15 2011 3 |
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A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. |
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A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. |
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A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. |
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Design and Implementation of a Configurable Real-Time FPGA-Based Geometric Symmetry-CFAR Processer for Radar Target Detection |
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https://doaj.org/article/193d2a2c67a6470986cb28ab3de3da88 https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1331 https://doaj.org/toc/2520-0917 https://doaj.org/toc/2520-0925 |
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