Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology

Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS tec...
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Autor*in:	Marshal Raj [verfasserIn] Lakshminarayanan Gopalakrishnan [verfasserIn] Seok‐Bum Ko [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	cellular automata hardware description languages logic gates nanoelectronics SRAM chips

Übergeordnetes Werk:	In: IET Computers & Digital Techniques - Wiley, 2021, 15(2021), 3, Seite 202-213
Übergeordnetes Werk:	volume:15 ; year:2021 ; number:3 ; pages:202-213

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc Journal toc

DOI / URN:	10.1049/cdt2.12012

Katalog-ID:	DOAJ08696481X

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520			\|a Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.
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allfields	10.1049/cdt2.12012 doi (DE-627)DOAJ08696481X (DE-599)DOAJf17774aa580741908792b0f4de0231a8 DE-627 ger DE-627 rakwb eng TK7885-7895 QA75.5-76.95 Marshal Raj verfasserin aut Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science Lakshminarayanan Gopalakrishnan verfasserin aut Seok‐Bum Ko verfasserin aut In IET Computers & Digital Techniques Wiley, 2021 15(2021), 3, Seite 202-213 (DE-627)521691605 (DE-600)2264236-5 1751861X nnns volume:15 year:2021 number:3 pages:202-213 https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/article/f17774aa580741908792b0f4de0231a8 kostenfrei https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/toc/1751-8601 Journal toc kostenfrei https://doaj.org/toc/1751-861X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_647 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2021 GBV_ILN_2026 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2088 GBV_ILN_2118 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 15 2021 3 202-213
spelling	10.1049/cdt2.12012 doi (DE-627)DOAJ08696481X (DE-599)DOAJf17774aa580741908792b0f4de0231a8 DE-627 ger DE-627 rakwb eng TK7885-7895 QA75.5-76.95 Marshal Raj verfasserin aut Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science Lakshminarayanan Gopalakrishnan verfasserin aut Seok‐Bum Ko verfasserin aut In IET Computers & Digital Techniques Wiley, 2021 15(2021), 3, Seite 202-213 (DE-627)521691605 (DE-600)2264236-5 1751861X nnns volume:15 year:2021 number:3 pages:202-213 https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/article/f17774aa580741908792b0f4de0231a8 kostenfrei https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/toc/1751-8601 Journal toc kostenfrei https://doaj.org/toc/1751-861X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_647 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2021 GBV_ILN_2026 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2088 GBV_ILN_2118 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 15 2021 3 202-213
allfields_unstemmed	10.1049/cdt2.12012 doi (DE-627)DOAJ08696481X (DE-599)DOAJf17774aa580741908792b0f4de0231a8 DE-627 ger DE-627 rakwb eng TK7885-7895 QA75.5-76.95 Marshal Raj verfasserin aut Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science Lakshminarayanan Gopalakrishnan verfasserin aut Seok‐Bum Ko verfasserin aut In IET Computers & Digital Techniques Wiley, 2021 15(2021), 3, Seite 202-213 (DE-627)521691605 (DE-600)2264236-5 1751861X nnns volume:15 year:2021 number:3 pages:202-213 https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/article/f17774aa580741908792b0f4de0231a8 kostenfrei https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/toc/1751-8601 Journal toc kostenfrei https://doaj.org/toc/1751-861X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_647 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2021 GBV_ILN_2026 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2088 GBV_ILN_2118 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 15 2021 3 202-213
allfieldsGer	10.1049/cdt2.12012 doi (DE-627)DOAJ08696481X (DE-599)DOAJf17774aa580741908792b0f4de0231a8 DE-627 ger DE-627 rakwb eng TK7885-7895 QA75.5-76.95 Marshal Raj verfasserin aut Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science Lakshminarayanan Gopalakrishnan verfasserin aut Seok‐Bum Ko verfasserin aut In IET Computers & Digital Techniques Wiley, 2021 15(2021), 3, Seite 202-213 (DE-627)521691605 (DE-600)2264236-5 1751861X nnns volume:15 year:2021 number:3 pages:202-213 https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/article/f17774aa580741908792b0f4de0231a8 kostenfrei https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/toc/1751-8601 Journal toc kostenfrei https://doaj.org/toc/1751-861X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_647 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2021 GBV_ILN_2026 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2088 GBV_ILN_2118 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 15 2021 3 202-213
allfieldsSound	10.1049/cdt2.12012 doi (DE-627)DOAJ08696481X (DE-599)DOAJf17774aa580741908792b0f4de0231a8 DE-627 ger DE-627 rakwb eng TK7885-7895 QA75.5-76.95 Marshal Raj verfasserin aut Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science Lakshminarayanan Gopalakrishnan verfasserin aut Seok‐Bum Ko verfasserin aut In IET Computers & Digital Techniques Wiley, 2021 15(2021), 3, Seite 202-213 (DE-627)521691605 (DE-600)2264236-5 1751861X nnns volume:15 year:2021 number:3 pages:202-213 https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/article/f17774aa580741908792b0f4de0231a8 kostenfrei https://doi.org/10.1049/cdt2.12012 kostenfrei https://doaj.org/toc/1751-8601 Journal toc kostenfrei https://doaj.org/toc/1751-861X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_647 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2021 GBV_ILN_2026 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2088 GBV_ILN_2118 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 15 2021 3 202-213
language	English
source	In IET Computers & Digital Techniques 15(2021), 3, Seite 202-213 volume:15 year:2021 number:3 pages:202-213
sourceStr	In IET Computers & Digital Techniques 15(2021), 3, Seite 202-213 volume:15 year:2021 number:3 pages:202-213
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	cellular automata hardware description languages logic gates nanoelectronics SRAM chips Computer engineering. Computer hardware Electronic computers. Computer science
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container_title	IET Computers & Digital Techniques
authorswithroles_txt_mv	Marshal Raj @@aut@@ Lakshminarayanan Gopalakrishnan @@aut@@ Seok‐Bum Ko @@aut@@
publishDateDaySort_date	2021-01-01T00:00:00Z
hierarchy_top_id	521691605
id	DOAJ08696481X
language_de	englisch
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callnumber-first	T - Technology
author	Marshal Raj
spellingShingle	Marshal Raj misc TK7885-7895 misc QA75.5-76.95 misc cellular automata misc hardware description languages misc logic gates misc nanoelectronics misc SRAM chips misc Computer engineering. Computer hardware misc Electronic computers. Computer science Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
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topic_title	TK7885-7895 QA75.5-76.95 Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology cellular automata hardware description languages logic gates nanoelectronics SRAM chips
topic	misc TK7885-7895 misc QA75.5-76.95 misc cellular automata misc hardware description languages misc logic gates misc nanoelectronics misc SRAM chips misc Computer engineering. Computer hardware misc Electronic computers. Computer science
topic_unstemmed	misc TK7885-7895 misc QA75.5-76.95 misc cellular automata misc hardware description languages misc logic gates misc nanoelectronics misc SRAM chips misc Computer engineering. Computer hardware misc Electronic computers. Computer science
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title	Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
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title_full	Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
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title_sort	reliable sram using nand‐nor gate in beyond‐cmos qca technology
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title_auth	Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
abstract	Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.
abstractGer	Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.
abstract_unstemmed	Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.
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title_short	Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
url	https://doi.org/10.1049/cdt2.12012 https://doaj.org/article/f17774aa580741908792b0f4de0231a8 https://doaj.org/toc/1751-8601 https://doaj.org/toc/1751-861X
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author2	Lakshminarayanan Gopalakrishnan Seok‐Bum Ko
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