A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle...
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Autor*in:	Ya Hai [verfasserIn] Fei Liu [verfasserIn] Yongshan Wang [verfasserIn] Jing Kang [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2023

Schlagwörter:	clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates

Übergeordnetes Werk:	In: Electronics Letters - Wiley, 2021, 59(2023), 8, Seite n/a-n/a
Übergeordnetes Werk:	volume:59 ; year:2023 ; number:8 ; pages:n/a-n/a

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc Journal toc

DOI / URN:	10.1049/ell2.12793

Katalog-ID:	DOAJ089930584

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520			\|a Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.
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allfields	10.1049/ell2.12793 doi (DE-627)DOAJ089930584 (DE-599)DOAJ84ff5ff2ed6644bf8f0b59c7d2cd1428 DE-627 ger DE-627 rakwb eng TK1-9971 Ya Hai verfasserin aut A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering Fei Liu verfasserin aut Yongshan Wang verfasserin aut Jing Kang verfasserin aut In Electronics Letters Wiley, 2021 59(2023), 8, Seite n/a-n/a (DE-627)325616094 (DE-600)2038620-5 1350911X nnns volume:59 year:2023 number:8 pages:n/a-n/a https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 kostenfrei https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/toc/0013-5194 Journal toc kostenfrei https://doaj.org/toc/1350-911X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 59 2023 8 n/a-n/a
spelling	10.1049/ell2.12793 doi (DE-627)DOAJ089930584 (DE-599)DOAJ84ff5ff2ed6644bf8f0b59c7d2cd1428 DE-627 ger DE-627 rakwb eng TK1-9971 Ya Hai verfasserin aut A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering Fei Liu verfasserin aut Yongshan Wang verfasserin aut Jing Kang verfasserin aut In Electronics Letters Wiley, 2021 59(2023), 8, Seite n/a-n/a (DE-627)325616094 (DE-600)2038620-5 1350911X nnns volume:59 year:2023 number:8 pages:n/a-n/a https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 kostenfrei https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/toc/0013-5194 Journal toc kostenfrei https://doaj.org/toc/1350-911X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 59 2023 8 n/a-n/a
allfields_unstemmed	10.1049/ell2.12793 doi (DE-627)DOAJ089930584 (DE-599)DOAJ84ff5ff2ed6644bf8f0b59c7d2cd1428 DE-627 ger DE-627 rakwb eng TK1-9971 Ya Hai verfasserin aut A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering Fei Liu verfasserin aut Yongshan Wang verfasserin aut Jing Kang verfasserin aut In Electronics Letters Wiley, 2021 59(2023), 8, Seite n/a-n/a (DE-627)325616094 (DE-600)2038620-5 1350911X nnns volume:59 year:2023 number:8 pages:n/a-n/a https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 kostenfrei https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/toc/0013-5194 Journal toc kostenfrei https://doaj.org/toc/1350-911X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 59 2023 8 n/a-n/a
allfieldsGer	10.1049/ell2.12793 doi (DE-627)DOAJ089930584 (DE-599)DOAJ84ff5ff2ed6644bf8f0b59c7d2cd1428 DE-627 ger DE-627 rakwb eng TK1-9971 Ya Hai verfasserin aut A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering Fei Liu verfasserin aut Yongshan Wang verfasserin aut Jing Kang verfasserin aut In Electronics Letters Wiley, 2021 59(2023), 8, Seite n/a-n/a (DE-627)325616094 (DE-600)2038620-5 1350911X nnns volume:59 year:2023 number:8 pages:n/a-n/a https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 kostenfrei https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/toc/0013-5194 Journal toc kostenfrei https://doaj.org/toc/1350-911X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 59 2023 8 n/a-n/a
allfieldsSound	10.1049/ell2.12793 doi (DE-627)DOAJ089930584 (DE-599)DOAJ84ff5ff2ed6644bf8f0b59c7d2cd1428 DE-627 ger DE-627 rakwb eng TK1-9971 Ya Hai verfasserin aut A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering Fei Liu verfasserin aut Yongshan Wang verfasserin aut Jing Kang verfasserin aut In Electronics Letters Wiley, 2021 59(2023), 8, Seite n/a-n/a (DE-627)325616094 (DE-600)2038620-5 1350911X nnns volume:59 year:2023 number:8 pages:n/a-n/a https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 kostenfrei https://doi.org/10.1049/ell2.12793 kostenfrei https://doaj.org/toc/0013-5194 Journal toc kostenfrei https://doaj.org/toc/1350-911X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2026 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 59 2023 8 n/a-n/a
language	English
source	In Electronics Letters 59(2023), 8, Seite n/a-n/a volume:59 year:2023 number:8 pages:n/a-n/a
sourceStr	In Electronics Letters 59(2023), 8, Seite n/a-n/a volume:59 year:2023 number:8 pages:n/a-n/a
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates Electrical engineering. Electronics. Nuclear engineering
isfreeaccess_bool	true
container_title	Electronics Letters
authorswithroles_txt_mv	Ya Hai @@aut@@ Fei Liu @@aut@@ Yongshan Wang @@aut@@ Jing Kang @@aut@@
publishDateDaySort_date	2023-01-01T00:00:00Z
hierarchy_top_id	325616094
id	DOAJ089930584
language_de	englisch
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callnumber-first	T - Technology
author	Ya Hai
spellingShingle	Ya Hai misc TK1-9971 misc clock distribution networks misc CMOS digital integrated circuits misc delay circuits misc error correction misc high‐speed integrated circuits misc logic gates misc Electrical engineering. Electronics. Nuclear engineering A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
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topic_title	TK1-9971 A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates
topic	misc TK1-9971 misc clock distribution networks misc CMOS digital integrated circuits misc delay circuits misc error correction misc high‐speed integrated circuits misc logic gates misc Electrical engineering. Electronics. Nuclear engineering
topic_unstemmed	misc TK1-9971 misc clock distribution networks misc CMOS digital integrated circuits misc delay circuits misc error correction misc high‐speed integrated circuits misc logic gates misc Electrical engineering. Electronics. Nuclear engineering
topic_browse	misc TK1-9971 misc clock distribution networks misc CMOS digital integrated circuits misc delay circuits misc error correction misc high‐speed integrated circuits misc logic gates misc Electrical engineering. Electronics. Nuclear engineering
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title	A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
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title_full	A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
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journal	Electronics Letters
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doi_str_mv	10.1049/ell2.12793
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title_sort	small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
callnumber	TK1-9971
title_auth	A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
abstract	Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.
abstractGer	Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.
abstract_unstemmed	Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.
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title_short	A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
url	https://doi.org/10.1049/ell2.12793 https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428 https://doaj.org/toc/0013-5194 https://doaj.org/toc/1350-911X
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up_date	2024-07-04T01:14:40.605Z
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A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

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