Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform

This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to su...
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Gespeichert in:

Autor*in:	Marc Majoral [verfasserIn] Javier Arribas [verfasserIn] Carles Fernández-Prades [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2024

Schlagwörter:	GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio

Übergeordnetes Werk:	In: Sensors - MDPI AG, 2003, 24(2024), 5, p 1416
Übergeordnetes Werk:	volume:24 ; year:2024 ; number:5, p 1416

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/s24051416

Katalog-ID:	DOAJ091235936

Internformat


LEADER	01000caa a22002652 4500
001	DOAJ091235936
003	DE-627
005	20240413232334.0
007	cr uuu---uuuuu
008	240412s2024 xx \|\|\|\|\|o 00\| \|\|eng c
024	7		\|a 10.3390/s24051416 \|2 doi
035			\|a (DE-627)DOAJ091235936
035			\|a (DE-599)DOAJbd403378dc964567938f55ebd0ae635c
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
041			\|a eng
050		0	\|a TP1-1185
100	0		\|a Marc Majoral \|e verfasserin \|4 aut
245	1	0	\|a Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
264		1	\|c 2024
336			\|a Text \|b txt \|2 rdacontent
337			\|a Computermedien \|b c \|2 rdamedia
338			\|a Online-Ressource \|b cr \|2 rdacarrier
520			\|a This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.
650		4	\|a GNSS
650		4	\|a FPGA
650		4	\|a system on chip
650		4	\|a SoC-FPGA
650		4	\|a high-sensitivity GNSS receiver
650		4	\|a software-defined radio
653		0	\|a Chemical technology
700	0		\|a Javier Arribas \|e verfasserin \|4 aut
700	0		\|a Carles Fernández-Prades \|e verfasserin \|4 aut
773	0	8	\|i In \|t Sensors \|d MDPI AG, 2003 \|g 24(2024), 5, p 1416 \|w (DE-627)331640910 \|w (DE-600)2052857-7 \|x 14248220 \|7 nnns
773	1	8	\|g volume:24 \|g year:2024 \|g number:5, p 1416
856	4	0	\|u https://doi.org/10.3390/s24051416 \|z kostenfrei
856	4	0	\|u https://doaj.org/article/bd403378dc964567938f55ebd0ae635c \|z kostenfrei
856	4	0	\|u https://www.mdpi.com/1424-8220/24/5/1416 \|z kostenfrei
856	4	2	\|u https://doaj.org/toc/1424-8220 \|y Journal toc \|z kostenfrei
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_DOAJ
912			\|a GBV_ILN_20
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_31
912			\|a GBV_ILN_39
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_63
912			\|a GBV_ILN_65
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_95
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_151
912			\|a GBV_ILN_161
912			\|a GBV_ILN_170
912			\|a GBV_ILN_206
912			\|a GBV_ILN_213
912			\|a GBV_ILN_230
912			\|a GBV_ILN_285
912			\|a GBV_ILN_293
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2009
912			\|a GBV_ILN_2011
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2055
912			\|a GBV_ILN_2057
912			\|a GBV_ILN_2111
912			\|a GBV_ILN_2507
912			\|a GBV_ILN_4012
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4126
912			\|a GBV_ILN_4249
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4325
912			\|a GBV_ILN_4335
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4367
912			\|a GBV_ILN_4700
951			\|a AR
952			\|d 24 \|j 2024 \|e 5, p 1416

Indexfelder

author_variant	m m mm j a ja c f p cfp
matchkey_str	article:14248220:2024----::mlmnainfhgsniiiylblaiainaeltssercieoaytmnhpil
hierarchy_sort_str	2024
callnumber-subject-code	TP
publishDate	2024
allfields	10.3390/s24051416 doi (DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c DE-627 ger DE-627 rakwb eng TP1-1185 Marc Majoral verfasserin aut Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform 2024 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology Javier Arribas verfasserin aut Carles Fernández-Prades verfasserin aut In Sensors MDPI AG, 2003 24(2024), 5, p 1416 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:24 year:2024 number:5, p 1416 https://doi.org/10.3390/s24051416 kostenfrei https://doaj.org/article/bd403378dc964567938f55ebd0ae635c kostenfrei https://www.mdpi.com/1424-8220/24/5/1416 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 24 2024 5, p 1416
spelling	10.3390/s24051416 doi (DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c DE-627 ger DE-627 rakwb eng TP1-1185 Marc Majoral verfasserin aut Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform 2024 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology Javier Arribas verfasserin aut Carles Fernández-Prades verfasserin aut In Sensors MDPI AG, 2003 24(2024), 5, p 1416 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:24 year:2024 number:5, p 1416 https://doi.org/10.3390/s24051416 kostenfrei https://doaj.org/article/bd403378dc964567938f55ebd0ae635c kostenfrei https://www.mdpi.com/1424-8220/24/5/1416 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 24 2024 5, p 1416
allfields_unstemmed	10.3390/s24051416 doi (DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c DE-627 ger DE-627 rakwb eng TP1-1185 Marc Majoral verfasserin aut Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform 2024 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology Javier Arribas verfasserin aut Carles Fernández-Prades verfasserin aut In Sensors MDPI AG, 2003 24(2024), 5, p 1416 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:24 year:2024 number:5, p 1416 https://doi.org/10.3390/s24051416 kostenfrei https://doaj.org/article/bd403378dc964567938f55ebd0ae635c kostenfrei https://www.mdpi.com/1424-8220/24/5/1416 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 24 2024 5, p 1416
allfieldsGer	10.3390/s24051416 doi (DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c DE-627 ger DE-627 rakwb eng TP1-1185 Marc Majoral verfasserin aut Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform 2024 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology Javier Arribas verfasserin aut Carles Fernández-Prades verfasserin aut In Sensors MDPI AG, 2003 24(2024), 5, p 1416 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:24 year:2024 number:5, p 1416 https://doi.org/10.3390/s24051416 kostenfrei https://doaj.org/article/bd403378dc964567938f55ebd0ae635c kostenfrei https://www.mdpi.com/1424-8220/24/5/1416 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 24 2024 5, p 1416
allfieldsSound	10.3390/s24051416 doi (DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c DE-627 ger DE-627 rakwb eng TP1-1185 Marc Majoral verfasserin aut Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform 2024 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology Javier Arribas verfasserin aut Carles Fernández-Prades verfasserin aut In Sensors MDPI AG, 2003 24(2024), 5, p 1416 (DE-627)331640910 (DE-600)2052857-7 14248220 nnns volume:24 year:2024 number:5, p 1416 https://doi.org/10.3390/s24051416 kostenfrei https://doaj.org/article/bd403378dc964567938f55ebd0ae635c kostenfrei https://www.mdpi.com/1424-8220/24/5/1416 kostenfrei https://doaj.org/toc/1424-8220 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 24 2024 5, p 1416
language	English
source	In Sensors 24(2024), 5, p 1416 volume:24 year:2024 number:5, p 1416
sourceStr	In Sensors 24(2024), 5, p 1416 volume:24 year:2024 number:5, p 1416
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio Chemical technology
isfreeaccess_bool	true
container_title	Sensors
authorswithroles_txt_mv	Marc Majoral @@aut@@ Javier Arribas @@aut@@ Carles Fernández-Prades @@aut@@
publishDateDaySort_date	2024-01-01T00:00:00Z
hierarchy_top_id	331640910
id	DOAJ091235936
language_de	englisch
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ091235936</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20240413232334.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">240412s2024 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.3390/s24051416</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ091235936</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJbd403378dc964567938f55ebd0ae635c</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TP1-1185</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Marc Majoral</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2024</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">GNSS</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FPGA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">system on chip</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">SoC-FPGA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">high-sensitivity GNSS receiver</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">software-defined radio</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Chemical technology</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Javier Arribas</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Carles Fernández-Prades</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Sensors</subfield><subfield code="d">MDPI AG, 2003</subfield><subfield code="g">24(2024), 5, p 1416</subfield><subfield code="w">(DE-627)331640910</subfield><subfield code="w">(DE-600)2052857-7</subfield><subfield code="x">14248220</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:24</subfield><subfield code="g">year:2024</subfield><subfield code="g">number:5, p 1416</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.3390/s24051416</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/bd403378dc964567938f55ebd0ae635c</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://www.mdpi.com/1424-8220/24/5/1416</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1424-8220</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_206</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4367</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">24</subfield><subfield code="j">2024</subfield><subfield code="e">5, p 1416</subfield></datafield></record></collection>
callnumber-first	T - Technology
author	Marc Majoral
spellingShingle	Marc Majoral misc TP1-1185 misc GNSS misc FPGA misc system on chip misc SoC-FPGA misc high-sensitivity GNSS receiver misc software-defined radio misc Chemical technology Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
authorStr	Marc Majoral
ppnlink_with_tag_str_mv	@@773@@(DE-627)331640910
format	electronic Article
delete_txt_mv	keep
author_role	aut aut aut
collection	DOAJ
remote_str	true
callnumber-label	TP1-1185
illustrated	Not Illustrated
issn	14248220
topic_title	TP1-1185 Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform GNSS FPGA system on chip SoC-FPGA high-sensitivity GNSS receiver software-defined radio
topic	misc TP1-1185 misc GNSS misc FPGA misc system on chip misc SoC-FPGA misc high-sensitivity GNSS receiver misc software-defined radio misc Chemical technology
topic_unstemmed	misc TP1-1185 misc GNSS misc FPGA misc system on chip misc SoC-FPGA misc high-sensitivity GNSS receiver misc software-defined radio misc Chemical technology
topic_browse	misc TP1-1185 misc GNSS misc FPGA misc system on chip misc SoC-FPGA misc high-sensitivity GNSS receiver misc software-defined radio misc Chemical technology
format_facet	Elektronische Aufsätze Aufsätze Elektronische Ressource
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	cr
hierarchy_parent_title	Sensors
hierarchy_parent_id	331640910
hierarchy_top_title	Sensors
isfreeaccess_txt	true
familylinks_str_mv	(DE-627)331640910 (DE-600)2052857-7
title	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
ctrlnum	(DE-627)DOAJ091235936 (DE-599)DOAJbd403378dc964567938f55ebd0ae635c
title_full	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
author_sort	Marc Majoral
journal	Sensors
journalStr	Sensors
callnumber-first-code	T
lang_code	eng
isOA_bool	true
recordtype	marc
publishDateSort	2024
contenttype_str_mv	txt
author_browse	Marc Majoral Javier Arribas Carles Fernández-Prades
container_volume	24
class	TP1-1185
format_se	Elektronische Aufsätze
author-letter	Marc Majoral
doi_str_mv	10.3390/s24051416
author2-role	verfasserin
title_sort	implementation of a high-sensitivity global navigation satellite system receiver on a system-on-chip field-programmable gate array platform
callnumber	TP1-1185
title_auth	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
abstract	This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.
abstractGer	This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.
abstract_unstemmed	This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_206 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2005 GBV_ILN_2009 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2111 GBV_ILN_2507 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700
container_issue	5, p 1416
title_short	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
url	https://doi.org/10.3390/s24051416 https://doaj.org/article/bd403378dc964567938f55ebd0ae635c https://www.mdpi.com/1424-8220/24/5/1416 https://doaj.org/toc/1424-8220
remote_bool	true
author2	Javier Arribas Carles Fernández-Prades
author2Str	Javier Arribas Carles Fernández-Prades
ppnlink	331640910
callnumber-subject	TP - Chemical Technology
mediatype_str_mv	c
isOA_txt	true
hochschulschrift_bool	false
doi_str	10.3390/s24051416
callnumber-a	TP1-1185
up_date	2024-07-03T19:16:19.539Z
_version_	1803586559848480768
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">DOAJ091235936</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20240413232334.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">240412s2024 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.3390/s24051416</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)DOAJ091235936</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DOAJbd403378dc964567938f55ebd0ae635c</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TP1-1185</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Marc Majoral</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2024</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (<inline-formula<<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"<<semantics<<mrow<<mi<C</mi<<mo</</mo<<msub<<mi<N</mi<<mn<0</mn<</msub<</mrow<</semantics<</math<</inline-formula<) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">GNSS</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FPGA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">system on chip</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">SoC-FPGA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">high-sensitivity GNSS receiver</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">software-defined radio</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Chemical technology</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Javier Arribas</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Carles Fernández-Prades</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">In</subfield><subfield code="t">Sensors</subfield><subfield code="d">MDPI AG, 2003</subfield><subfield code="g">24(2024), 5, p 1416</subfield><subfield code="w">(DE-627)331640910</subfield><subfield code="w">(DE-600)2052857-7</subfield><subfield code="x">14248220</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:24</subfield><subfield code="g">year:2024</subfield><subfield code="g">number:5, p 1416</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.3390/s24051416</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doaj.org/article/bd403378dc964567938f55ebd0ae635c</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://www.mdpi.com/1424-8220/24/5/1416</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">https://doaj.org/toc/1424-8220</subfield><subfield code="y">Journal toc</subfield><subfield code="z">kostenfrei</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_DOAJ</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_206</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4367</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">24</subfield><subfield code="j">2024</subfield><subfield code="e">5, p 1416</subfield></datafield></record></collection>
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Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform

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