The Design of a Dynamic Configurable Packet Parser Based on FPGA

To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is redu...
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Autor*in:	Ying Sun [verfasserIn] Zhichuan Guo [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2023

Schlagwörter:	FPGA packet parser dynamic configurable low lantency

Übergeordnetes Werk:	In: Micromachines - MDPI AG, 2010, 14(2023), 8, p 1560
Übergeordnetes Werk:	volume:14 ; year:2023 ; number:8, p 1560

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/mi14081560

Katalog-ID:	DOAJ093578628

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allfieldsSound	10.3390/mi14081560 doi (DE-627)DOAJ093578628 (DE-599)DOAJ8f428516378147b79c8571ff33f8e6f4 DE-627 ger DE-627 rakwb eng TJ1-1570 Ying Sun verfasserin aut The Design of a Dynamic Configurable Packet Parser Based on FPGA 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing. FPGA packet parser dynamic configurable low lantency Mechanical engineering and machinery Zhichuan Guo verfasserin aut In Micromachines MDPI AG, 2010 14(2023), 8, p 1560 (DE-627)665016069 (DE-600)2620864-7 2072666X nnns volume:14 year:2023 number:8, p 1560 https://doi.org/10.3390/mi14081560 kostenfrei https://doaj.org/article/8f428516378147b79c8571ff33f8e6f4 kostenfrei https://www.mdpi.com/2072-666X/14/8/1560 kostenfrei https://doaj.org/toc/2072-666X Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 14 2023 8, p 1560
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source	In Micromachines 14(2023), 8, p 1560 volume:14 year:2023 number:8, p 1560
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authorswithroles_txt_mv	Ying Sun @@aut@@ Zhichuan Guo @@aut@@
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callnumber-first	T - Technology
author	Ying Sun
spellingShingle	Ying Sun misc TJ1-1570 misc FPGA misc packet parser misc dynamic configurable misc low lantency misc Mechanical engineering and machinery The Design of a Dynamic Configurable Packet Parser Based on FPGA
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topic_title	TJ1-1570 The Design of a Dynamic Configurable Packet Parser Based on FPGA FPGA packet parser dynamic configurable low lantency
topic	misc TJ1-1570 misc FPGA misc packet parser misc dynamic configurable misc low lantency misc Mechanical engineering and machinery
topic_unstemmed	misc TJ1-1570 misc FPGA misc packet parser misc dynamic configurable misc low lantency misc Mechanical engineering and machinery
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title	The Design of a Dynamic Configurable Packet Parser Based on FPGA
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title_sort	design of a dynamic configurable packet parser based on fpga
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title_auth	The Design of a Dynamic Configurable Packet Parser Based on FPGA
abstract	To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.
abstractGer	To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.
abstract_unstemmed	To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.
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