Cross-Mesh Clock Network Synthesis

In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh a...
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Autor*in:	Wei-Kai Cheng [verfasserIn] Zih-Ming Yeh [verfasserIn] Hsu-Yu Kao [verfasserIn] Shih-Hsu Huang [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2023

Schlagwörter:	clock mesh clock tree clock skew clock gating register clustering

Übergeordnetes Werk:	In: Electronics - MDPI AG, 2013, 12(2023), 16, p 3410
Übergeordnetes Werk:	volume:12 ; year:2023 ; number:16, p 3410

Links:	Link aufrufen Link aufrufen Link aufrufen Journal toc

DOI / URN:	10.3390/electronics12163410

Katalog-ID:	DOAJ093626134

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520			\|a In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.
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spelling	10.3390/electronics12163410 doi (DE-627)DOAJ093626134 (DE-599)DOAJ74e744cb644749c5b5e3f82546f3b718 DE-627 ger DE-627 rakwb eng TK7800-8360 Wei-Kai Cheng verfasserin aut Cross-Mesh Clock Network Synthesis 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously. clock mesh clock tree clock skew clock gating register clustering Electronics Zih-Ming Yeh verfasserin aut Hsu-Yu Kao verfasserin aut Shih-Hsu Huang verfasserin aut In Electronics MDPI AG, 2013 12(2023), 16, p 3410 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:12 year:2023 number:16, p 3410 https://doi.org/10.3390/electronics12163410 kostenfrei https://doaj.org/article/74e744cb644749c5b5e3f82546f3b718 kostenfrei https://www.mdpi.com/2079-9292/12/16/3410 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 12 2023 16, p 3410
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language	English
source	In Electronics 12(2023), 16, p 3410 volume:12 year:2023 number:16, p 3410
sourceStr	In Electronics 12(2023), 16, p 3410 volume:12 year:2023 number:16, p 3410
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callnumber-first	T - Technology
author	Wei-Kai Cheng
spellingShingle	Wei-Kai Cheng misc TK7800-8360 misc clock mesh misc clock tree misc clock skew misc clock gating misc register clustering misc Electronics Cross-Mesh Clock Network Synthesis
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topic_title	TK7800-8360 Cross-Mesh Clock Network Synthesis clock mesh clock tree clock skew clock gating register clustering
topic	misc TK7800-8360 misc clock mesh misc clock tree misc clock skew misc clock gating misc register clustering misc Electronics
topic_unstemmed	misc TK7800-8360 misc clock mesh misc clock tree misc clock skew misc clock gating misc register clustering misc Electronics
topic_browse	misc TK7800-8360 misc clock mesh misc clock tree misc clock skew misc clock gating misc register clustering misc Electronics
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title	Cross-Mesh Clock Network Synthesis
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title_sort	cross-mesh clock network synthesis
callnumber	TK7800-8360
title_auth	Cross-Mesh Clock Network Synthesis
abstract	In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.
abstractGer	In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.
abstract_unstemmed	In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.
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title_short	Cross-Mesh Clock Network Synthesis
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