CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion
In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell...
Ausführliche Beschreibung
Autor*in: |
Jesus E. Molinar-Solis [verfasserIn] Ivan Padilla-Cantoya [verfasserIn] Juan J. Ocampo-Hidalgo [verfasserIn] Sergio Sandoval-Perez [verfasserIn] Jose Rivera-Mejia [verfasserIn] |
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E-Artikel |
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Sprache: |
Englisch |
Erschienen: |
2023 |
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Übergeordnetes Werk: |
In: Electronics - MDPI AG, 2013, 12(2023), 16, p 3376 |
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Übergeordnetes Werk: |
volume:12 ; year:2023 ; number:16, p 3376 |
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DOI / URN: |
10.3390/electronics12163376 |
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Katalog-ID: |
DOAJ093626479 |
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10.3390/electronics12163376 doi (DE-627)DOAJ093626479 (DE-599)DOAJ9e05f974785a4a498d878e2558ec7636 DE-627 ger DE-627 rakwb eng TK7800-8360 Jesus E. Molinar-Solis verfasserin aut CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. CMOS analog integrated circuits filter integrated circuit design Electronics Ivan Padilla-Cantoya verfasserin aut Juan J. Ocampo-Hidalgo verfasserin aut Sergio Sandoval-Perez verfasserin aut Jose Rivera-Mejia verfasserin aut In Electronics MDPI AG, 2013 12(2023), 16, p 3376 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:12 year:2023 number:16, p 3376 https://doi.org/10.3390/electronics12163376 kostenfrei https://doaj.org/article/9e05f974785a4a498d878e2558ec7636 kostenfrei https://www.mdpi.com/2079-9292/12/16/3376 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 12 2023 16, p 3376 |
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10.3390/electronics12163376 doi (DE-627)DOAJ093626479 (DE-599)DOAJ9e05f974785a4a498d878e2558ec7636 DE-627 ger DE-627 rakwb eng TK7800-8360 Jesus E. Molinar-Solis verfasserin aut CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. CMOS analog integrated circuits filter integrated circuit design Electronics Ivan Padilla-Cantoya verfasserin aut Juan J. Ocampo-Hidalgo verfasserin aut Sergio Sandoval-Perez verfasserin aut Jose Rivera-Mejia verfasserin aut In Electronics MDPI AG, 2013 12(2023), 16, p 3376 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:12 year:2023 number:16, p 3376 https://doi.org/10.3390/electronics12163376 kostenfrei https://doaj.org/article/9e05f974785a4a498d878e2558ec7636 kostenfrei https://www.mdpi.com/2079-9292/12/16/3376 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 12 2023 16, p 3376 |
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10.3390/electronics12163376 doi (DE-627)DOAJ093626479 (DE-599)DOAJ9e05f974785a4a498d878e2558ec7636 DE-627 ger DE-627 rakwb eng TK7800-8360 Jesus E. Molinar-Solis verfasserin aut CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. CMOS analog integrated circuits filter integrated circuit design Electronics Ivan Padilla-Cantoya verfasserin aut Juan J. Ocampo-Hidalgo verfasserin aut Sergio Sandoval-Perez verfasserin aut Jose Rivera-Mejia verfasserin aut In Electronics MDPI AG, 2013 12(2023), 16, p 3376 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:12 year:2023 number:16, p 3376 https://doi.org/10.3390/electronics12163376 kostenfrei https://doaj.org/article/9e05f974785a4a498d878e2558ec7636 kostenfrei https://www.mdpi.com/2079-9292/12/16/3376 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 12 2023 16, p 3376 |
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10.3390/electronics12163376 doi (DE-627)DOAJ093626479 (DE-599)DOAJ9e05f974785a4a498d878e2558ec7636 DE-627 ger DE-627 rakwb eng TK7800-8360 Jesus E. Molinar-Solis verfasserin aut CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. CMOS analog integrated circuits filter integrated circuit design Electronics Ivan Padilla-Cantoya verfasserin aut Juan J. Ocampo-Hidalgo verfasserin aut Sergio Sandoval-Perez verfasserin aut Jose Rivera-Mejia verfasserin aut In Electronics MDPI AG, 2013 12(2023), 16, p 3376 (DE-627)718626478 (DE-600)2662127-7 20799292 nnns volume:12 year:2023 number:16, p 3376 https://doi.org/10.3390/electronics12163376 kostenfrei https://doaj.org/article/9e05f974785a4a498d878e2558ec7636 kostenfrei https://www.mdpi.com/2079-9292/12/16/3376 kostenfrei https://doaj.org/toc/2079-9292 Journal toc kostenfrei GBV_USEFLAG_A SYSFLAG_A GBV_DOAJ GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_95 GBV_ILN_105 GBV_ILN_110 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_213 GBV_ILN_230 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_2014 GBV_ILN_4012 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4249 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4367 GBV_ILN_4700 AR 12 2023 16, p 3376 |
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In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. |
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In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. |
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In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V<sub<p</sub<. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility. |
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|
score |
7.400091 |