FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping

Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension o...
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Autor*in:	Soliman, Shady [verfasserIn] Jaela, Mohammed A. [verfasserIn] Abotaleb, Abdelrhman M. [verfasserIn] Hassan, Youssef [verfasserIn] Abdelghany, Mohamed A. [verfasserIn] Abdel-Hamid, Amr T. [verfasserIn] Salama, Khaled N. [verfasserIn] Mostafa, Hassan [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2019

Schlagwörter:	CAESAR FPGA DPR Cryptography Hopping AEAD IoT

Übergeordnetes Werk:	Enthalten in: Integration, the VLSI journal - Amsterdam [u.a.] : Elsevier Science, 1983, 68, Seite 108-121
Übergeordnetes Werk:	volume:68 ; pages:108-121

DOI / URN:	10.1016/j.vlsi.2019.06.004

Katalog-ID:	ELV002657139

Internformat


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100	1		\|a Soliman, Shady \|e verfasserin \|4 aut
245	1	0	\|a FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
264		1	\|c 2019
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337			\|a Computermedien \|b c \|2 rdamedia
338			\|a Online-Ressource \|b cr \|2 rdacarrier
520			\|a Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
650		4	\|a CAESAR
650		4	\|a FPGA
650		4	\|a DPR
650		4	\|a Cryptography
650		4	\|a Hopping
650		4	\|a AEAD
650		4	\|a IoT
700	1		\|a Jaela, Mohammed A. \|e verfasserin \|4 aut
700	1		\|a Abotaleb, Abdelrhman M. \|e verfasserin \|4 aut
700	1		\|a Hassan, Youssef \|e verfasserin \|4 aut
700	1		\|a Abdelghany, Mohamed A. \|e verfasserin \|4 aut
700	1		\|a Abdel-Hamid, Amr T. \|e verfasserin \|4 aut
700	1		\|a Salama, Khaled N. \|e verfasserin \|4 aut
700	1		\|a Mostafa, Hassan \|e verfasserin \|4 aut
773	0	8	\|i Enthalten in \|t Integration, the VLSI journal \|d Amsterdam [u.a.] : Elsevier Science, 1983 \|g 68, Seite 108-121 \|h Online-Ressource \|w (DE-627)32043012X \|w (DE-600)2003659-0 \|w (DE-576)114818045 \|7 nnns
773	1	8	\|g volume:68 \|g pages:108-121
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912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_31
912			\|a GBV_ILN_32
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_63
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_74
912			\|a GBV_ILN_90
912			\|a GBV_ILN_95
912			\|a GBV_ILN_100
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_150
912			\|a GBV_ILN_151
912			\|a GBV_ILN_224
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_702
912			\|a GBV_ILN_2001
912			\|a GBV_ILN_2003
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2008
912			\|a GBV_ILN_2010
912			\|a GBV_ILN_2011
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2015
912			\|a GBV_ILN_2020
912			\|a GBV_ILN_2021
912			\|a GBV_ILN_2025
912			\|a GBV_ILN_2026
912			\|a GBV_ILN_2027
912			\|a GBV_ILN_2034
912			\|a GBV_ILN_2038
912			\|a GBV_ILN_2044
912			\|a GBV_ILN_2048
912			\|a GBV_ILN_2049
912			\|a GBV_ILN_2050
912			\|a GBV_ILN_2055
912			\|a GBV_ILN_2056
912			\|a GBV_ILN_2059
912			\|a GBV_ILN_2061
912			\|a GBV_ILN_2064
912			\|a GBV_ILN_2065
912			\|a GBV_ILN_2068
912			\|a GBV_ILN_2088
912			\|a GBV_ILN_2111
912			\|a GBV_ILN_2112
912			\|a GBV_ILN_2113
912			\|a GBV_ILN_2118
912			\|a GBV_ILN_2122
912			\|a GBV_ILN_2129
912			\|a GBV_ILN_2143
912			\|a GBV_ILN_2147
912			\|a GBV_ILN_2148
912			\|a GBV_ILN_2152
912			\|a GBV_ILN_2153
912			\|a GBV_ILN_2190
912			\|a GBV_ILN_2232
912			\|a GBV_ILN_2336
912			\|a GBV_ILN_2470
912			\|a GBV_ILN_2507
912			\|a GBV_ILN_2522
912			\|a GBV_ILN_4035
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4046
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4126
912			\|a GBV_ILN_4242
912			\|a GBV_ILN_4251
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4326
912			\|a GBV_ILN_4333
912			\|a GBV_ILN_4334
912			\|a GBV_ILN_4335
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4393
936	b	k	\|a 31.00 \|j Mathematik: Allgemeines
951			\|a AR
952			\|d 68 \|h 108-121

Indexfelder

author_variant	s s ss m a j ma maj a m a am ama y h yh m a a ma maa a t a h ata atah k n s kn kns h m hm
matchkey_str	solimanshadyjaelamohammedaabotalebabdelr:2019----:pamlmnainfyaialrcniualiteuiyou
hierarchy_sort_str	2019
bklnumber	31.00
publishDate	2019
allfields	10.1016/j.vlsi.2019.06.004 doi (DE-627)ELV002657139 (ELSEVIER)S0167-9260(19)30053-7 DE-627 ger DE-627 rda eng 510 DE-600 31.00 bkl Soliman, Shady verfasserin aut FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping 2019 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). CAESAR FPGA DPR Cryptography Hopping AEAD IoT Jaela, Mohammed A. verfasserin aut Abotaleb, Abdelrhman M. verfasserin aut Hassan, Youssef verfasserin aut Abdelghany, Mohamed A. verfasserin aut Abdel-Hamid, Amr T. verfasserin aut Salama, Khaled N. verfasserin aut Mostafa, Hassan verfasserin aut Enthalten in Integration, the VLSI journal Amsterdam [u.a.] : Elsevier Science, 1983 68, Seite 108-121 Online-Ressource (DE-627)32043012X (DE-600)2003659-0 (DE-576)114818045 nnns volume:68 pages:108-121 GBV_USEFLAG_U SYSFLAG_U GBV_ELV GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_224 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2008 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4393 31.00 Mathematik: Allgemeines AR 68 108-121
spelling	10.1016/j.vlsi.2019.06.004 doi (DE-627)ELV002657139 (ELSEVIER)S0167-9260(19)30053-7 DE-627 ger DE-627 rda eng 510 DE-600 31.00 bkl Soliman, Shady verfasserin aut FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping 2019 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). CAESAR FPGA DPR Cryptography Hopping AEAD IoT Jaela, Mohammed A. verfasserin aut Abotaleb, Abdelrhman M. verfasserin aut Hassan, Youssef verfasserin aut Abdelghany, Mohamed A. verfasserin aut Abdel-Hamid, Amr T. verfasserin aut Salama, Khaled N. verfasserin aut Mostafa, Hassan verfasserin aut Enthalten in Integration, the VLSI journal Amsterdam [u.a.] : Elsevier Science, 1983 68, Seite 108-121 Online-Ressource (DE-627)32043012X (DE-600)2003659-0 (DE-576)114818045 nnns volume:68 pages:108-121 GBV_USEFLAG_U SYSFLAG_U GBV_ELV GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_224 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2008 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4393 31.00 Mathematik: Allgemeines AR 68 108-121
allfields_unstemmed	10.1016/j.vlsi.2019.06.004 doi (DE-627)ELV002657139 (ELSEVIER)S0167-9260(19)30053-7 DE-627 ger DE-627 rda eng 510 DE-600 31.00 bkl Soliman, Shady verfasserin aut FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping 2019 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). CAESAR FPGA DPR Cryptography Hopping AEAD IoT Jaela, Mohammed A. verfasserin aut Abotaleb, Abdelrhman M. verfasserin aut Hassan, Youssef verfasserin aut Abdelghany, Mohamed A. verfasserin aut Abdel-Hamid, Amr T. verfasserin aut Salama, Khaled N. verfasserin aut Mostafa, Hassan verfasserin aut Enthalten in Integration, the VLSI journal Amsterdam [u.a.] : Elsevier Science, 1983 68, Seite 108-121 Online-Ressource (DE-627)32043012X (DE-600)2003659-0 (DE-576)114818045 nnns volume:68 pages:108-121 GBV_USEFLAG_U SYSFLAG_U GBV_ELV GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_224 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2008 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4393 31.00 Mathematik: Allgemeines AR 68 108-121
allfieldsGer	10.1016/j.vlsi.2019.06.004 doi (DE-627)ELV002657139 (ELSEVIER)S0167-9260(19)30053-7 DE-627 ger DE-627 rda eng 510 DE-600 31.00 bkl Soliman, Shady verfasserin aut FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping 2019 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). CAESAR FPGA DPR Cryptography Hopping AEAD IoT Jaela, Mohammed A. verfasserin aut Abotaleb, Abdelrhman M. verfasserin aut Hassan, Youssef verfasserin aut Abdelghany, Mohamed A. verfasserin aut Abdel-Hamid, Amr T. verfasserin aut Salama, Khaled N. verfasserin aut Mostafa, Hassan verfasserin aut Enthalten in Integration, the VLSI journal Amsterdam [u.a.] : Elsevier Science, 1983 68, Seite 108-121 Online-Ressource (DE-627)32043012X (DE-600)2003659-0 (DE-576)114818045 nnns volume:68 pages:108-121 GBV_USEFLAG_U SYSFLAG_U GBV_ELV GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_224 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2008 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4393 31.00 Mathematik: Allgemeines AR 68 108-121
allfieldsSound	10.1016/j.vlsi.2019.06.004 doi (DE-627)ELV002657139 (ELSEVIER)S0167-9260(19)30053-7 DE-627 ger DE-627 rda eng 510 DE-600 31.00 bkl Soliman, Shady verfasserin aut FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping 2019 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). CAESAR FPGA DPR Cryptography Hopping AEAD IoT Jaela, Mohammed A. verfasserin aut Abotaleb, Abdelrhman M. verfasserin aut Hassan, Youssef verfasserin aut Abdelghany, Mohamed A. verfasserin aut Abdel-Hamid, Amr T. verfasserin aut Salama, Khaled N. verfasserin aut Mostafa, Hassan verfasserin aut Enthalten in Integration, the VLSI journal Amsterdam [u.a.] : Elsevier Science, 1983 68, Seite 108-121 Online-Ressource (DE-627)32043012X (DE-600)2003659-0 (DE-576)114818045 nnns volume:68 pages:108-121 GBV_USEFLAG_U SYSFLAG_U GBV_ELV GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_224 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2008 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2038 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4338 GBV_ILN_4393 31.00 Mathematik: Allgemeines AR 68 108-121
language	English
source	Enthalten in Integration, the VLSI journal 68, Seite 108-121 volume:68 pages:108-121
sourceStr	Enthalten in Integration, the VLSI journal 68, Seite 108-121 volume:68 pages:108-121
format_phy_str_mv	Article
bklname	Mathematik: Allgemeines
institution	findex.gbv.de
topic_facet	CAESAR FPGA DPR Cryptography Hopping AEAD IoT
dewey-raw	510
isfreeaccess_bool	false
container_title	Integration, the VLSI journal
authorswithroles_txt_mv	Soliman, Shady @@aut@@ Jaela, Mohammed A. @@aut@@ Abotaleb, Abdelrhman M. @@aut@@ Hassan, Youssef @@aut@@ Abdelghany, Mohamed A. @@aut@@ Abdel-Hamid, Amr T. @@aut@@ Salama, Khaled N. @@aut@@ Mostafa, Hassan @@aut@@
publishDateDaySort_date	2019-01-01T00:00:00Z
hierarchy_top_id	32043012X
dewey-sort	3510
id	ELV002657139
language_de	englisch
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author	Soliman, Shady
spellingShingle	Soliman, Shady ddc 510 bkl 31.00 misc CAESAR misc FPGA misc DPR misc Cryptography misc Hopping misc AEAD misc IoT FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
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topic_title	510 DE-600 31.00 bkl FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping CAESAR FPGA DPR Cryptography Hopping AEAD IoT
topic	ddc 510 bkl 31.00 misc CAESAR misc FPGA misc DPR misc Cryptography misc Hopping misc AEAD misc IoT
topic_unstemmed	ddc 510 bkl 31.00 misc CAESAR misc FPGA misc DPR misc Cryptography misc Hopping misc AEAD misc IoT
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title	FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
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title_full	FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
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author_browse	Soliman, Shady Jaela, Mohammed A. Abotaleb, Abdelrhman M. Hassan, Youssef Abdelghany, Mohamed A. Abdel-Hamid, Amr T. Salama, Khaled N. Mostafa, Hassan
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title_sort	fpga implementation of dynamically reconfigurable iot security module using algorithm hopping
title_auth	FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
abstract	Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
abstractGer	Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
abstract_unstemmed	Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
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title_short	FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
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author2	Jaela, Mohammed A. Abotaleb, Abdelrhman M. Hassan, Youssef Abdelghany, Mohamed A. Abdel-Hamid, Amr T. Salama, Khaled N. Mostafa, Hassan
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up_date	2024-07-06T17:00:37.470Z
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FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping

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