A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non...
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Autor*in:	Samanta, Smrutilekha [verfasserIn] Sarkar, Santanu [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2023

Schlagwörter:	Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM

Systematik:	ZG 1100

Übergeordnetes Werk:	Enthalten in: International journal of electronics and communications - München : Elsevier, 2011, 161
Übergeordnetes Werk:	volume:161

DOI / URN:	10.1016/j.aeue.2023.154528

Katalog-ID:	ELV009228373

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100	1		\|a Samanta, Smrutilekha \|e verfasserin \|0 (orcid)0000-0001-9631-372X \|4 aut
245	1	0	\|a A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
264		1	\|c 2023
336			\|a nicht spezifiziert \|b zzz \|2 rdacontent
337			\|a Computermedien \|b c \|2 rdamedia
338			\|a Online-Ressource \|b cr \|2 rdacarrier
520			\|a This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.
650		4	\|a Current Steering DAC
650		4	\|a Dynamic element matching
650		4	\|a Code dependent load variation
650		4	\|a Output impedance
650		4	\|a Fully Random Rotation-based DEM
700	1		\|a Sarkar, Santanu \|e verfasserin \|4 aut
773	0	8	\|i Enthalten in \|t International journal of electronics and communications \|d München : Elsevier, 2011 \|g 161 \|w (DE-627)329270273 \|w (DE-600)2046900-7 \|x 143-48411 \|7 nnns
773	1	8	\|g volume:161
912			\|a GBV_USEFLAG_U
912			\|a SYSFLAG_U
912			\|a GBV_ELV
912			\|a SSG-OLC-TEC
912			\|a SSG-OLC-MAT
912			\|a GBV_ILN_20
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_31
912			\|a GBV_ILN_32
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_65
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_74
912			\|a GBV_ILN_90
912			\|a GBV_ILN_95
912			\|a GBV_ILN_100
912			\|a GBV_ILN_101
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_150
912			\|a GBV_ILN_151
912			\|a GBV_ILN_187
912			\|a GBV_ILN_213
912			\|a GBV_ILN_224
912			\|a GBV_ILN_230
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_702
912			\|a GBV_ILN_2001
912			\|a GBV_ILN_2003
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2007
912			\|a GBV_ILN_2008
912			\|a GBV_ILN_2009
912			\|a GBV_ILN_2010
912			\|a GBV_ILN_2011
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2015
912			\|a GBV_ILN_2020
912			\|a GBV_ILN_2021
912			\|a GBV_ILN_2025
912			\|a GBV_ILN_2026
912			\|a GBV_ILN_2027
912			\|a GBV_ILN_2034
912			\|a GBV_ILN_2044
912			\|a GBV_ILN_2048
912			\|a GBV_ILN_2049
912			\|a GBV_ILN_2050
912			\|a GBV_ILN_2055
912			\|a GBV_ILN_2056
912			\|a GBV_ILN_2059
912			\|a GBV_ILN_2061
912			\|a GBV_ILN_2064
912			\|a GBV_ILN_2088
912			\|a GBV_ILN_2106
912			\|a GBV_ILN_2110
912			\|a GBV_ILN_2111
912			\|a GBV_ILN_2112
912			\|a GBV_ILN_2122
912			\|a GBV_ILN_2129
912			\|a GBV_ILN_2143
912			\|a GBV_ILN_2152
912			\|a GBV_ILN_2153
912			\|a GBV_ILN_2190
912			\|a GBV_ILN_2232
912			\|a GBV_ILN_2336
912			\|a GBV_ILN_2470
912			\|a GBV_ILN_2507
912			\|a GBV_ILN_4035
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4242
912			\|a GBV_ILN_4249
912			\|a GBV_ILN_4251
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4325
912			\|a GBV_ILN_4326
912			\|a GBV_ILN_4333
912			\|a GBV_ILN_4334
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4393
912			\|a GBV_ILN_4700
936	r	v	\|a ZG 1100
936	b	k	\|a 53.70
936	b	k	\|a 53.72
936	b	k	\|a 53.73
936	b	k	\|a 53.74
936	b	k	\|a 53.75
936	b	k	\|a 53.76
951			\|a AR
952			\|d 161

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bklnumber	53.70 53.72 53.73 53.74 53.75 53.76
publishDate	2023
allfields	10.1016/j.aeue.2023.154528 doi (DE-627)ELV009228373 (ELSEVIER)S1434-8411(23)00002-X DE-627 ger DE-627 rda eng 004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl Samanta, Smrutilekha verfasserin (orcid)0000-0001-9631-372X aut A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation 2023 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply. Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM Sarkar, Santanu verfasserin aut Enthalten in International journal of electronics and communications München : Elsevier, 2011 161 (DE-627)329270273 (DE-600)2046900-7 143-48411 nnns volume:161 GBV_USEFLAG_U SYSFLAG_U GBV_ELV SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 ZG 1100 53.70 53.72 53.73 53.74 53.75 53.76 AR 161
spelling	10.1016/j.aeue.2023.154528 doi (DE-627)ELV009228373 (ELSEVIER)S1434-8411(23)00002-X DE-627 ger DE-627 rda eng 004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl Samanta, Smrutilekha verfasserin (orcid)0000-0001-9631-372X aut A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation 2023 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply. Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM Sarkar, Santanu verfasserin aut Enthalten in International journal of electronics and communications München : Elsevier, 2011 161 (DE-627)329270273 (DE-600)2046900-7 143-48411 nnns volume:161 GBV_USEFLAG_U SYSFLAG_U GBV_ELV SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 ZG 1100 53.70 53.72 53.73 53.74 53.75 53.76 AR 161
allfields_unstemmed	10.1016/j.aeue.2023.154528 doi (DE-627)ELV009228373 (ELSEVIER)S1434-8411(23)00002-X DE-627 ger DE-627 rda eng 004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl Samanta, Smrutilekha verfasserin (orcid)0000-0001-9631-372X aut A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation 2023 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply. Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM Sarkar, Santanu verfasserin aut Enthalten in International journal of electronics and communications München : Elsevier, 2011 161 (DE-627)329270273 (DE-600)2046900-7 143-48411 nnns volume:161 GBV_USEFLAG_U SYSFLAG_U GBV_ELV SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 ZG 1100 53.70 53.72 53.73 53.74 53.75 53.76 AR 161
allfieldsGer	10.1016/j.aeue.2023.154528 doi (DE-627)ELV009228373 (ELSEVIER)S1434-8411(23)00002-X DE-627 ger DE-627 rda eng 004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl Samanta, Smrutilekha verfasserin (orcid)0000-0001-9631-372X aut A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation 2023 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply. Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM Sarkar, Santanu verfasserin aut Enthalten in International journal of electronics and communications München : Elsevier, 2011 161 (DE-627)329270273 (DE-600)2046900-7 143-48411 nnns volume:161 GBV_USEFLAG_U SYSFLAG_U GBV_ELV SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 ZG 1100 53.70 53.72 53.73 53.74 53.75 53.76 AR 161
allfieldsSound	10.1016/j.aeue.2023.154528 doi (DE-627)ELV009228373 (ELSEVIER)S1434-8411(23)00002-X DE-627 ger DE-627 rda eng 004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl Samanta, Smrutilekha verfasserin (orcid)0000-0001-9631-372X aut A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation 2023 nicht spezifiziert zzz rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply. Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM Sarkar, Santanu verfasserin aut Enthalten in International journal of electronics and communications München : Elsevier, 2011 161 (DE-627)329270273 (DE-600)2046900-7 143-48411 nnns volume:161 GBV_USEFLAG_U SYSFLAG_U GBV_ELV SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_150 GBV_ILN_151 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2034 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2088 GBV_ILN_2106 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2470 GBV_ILN_2507 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 ZG 1100 53.70 53.72 53.73 53.74 53.75 53.76 AR 161
language	English
source	Enthalten in International journal of electronics and communications 161 volume:161
sourceStr	Enthalten in International journal of electronics and communications 161 volume:161
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM
dewey-raw	004
isfreeaccess_bool	false
container_title	International journal of electronics and communications
authorswithroles_txt_mv	Samanta, Smrutilekha @@aut@@ Sarkar, Santanu @@aut@@
publishDateDaySort_date	2023-01-01T00:00:00Z
hierarchy_top_id	329270273
dewey-sort	14
id	ELV009228373
language_de	englisch
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author	Samanta, Smrutilekha
spellingShingle	Samanta, Smrutilekha ddc 004 sdnb 37 rvk ZG 1100 bkl 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 misc Current Steering DAC misc Dynamic element matching misc Code dependent load variation misc Output impedance misc Fully Random Rotation-based DEM A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
authorStr	Samanta, Smrutilekha
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topic_title	004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation Current Steering DAC Dynamic element matching Code dependent load variation Output impedance Fully Random Rotation-based DEM
topic	ddc 004 sdnb 37 rvk ZG 1100 bkl 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 misc Current Steering DAC misc Dynamic element matching misc Code dependent load variation misc Output impedance misc Fully Random Rotation-based DEM
topic_unstemmed	ddc 004 sdnb 37 rvk ZG 1100 bkl 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 misc Current Steering DAC misc Dynamic element matching misc Code dependent load variation misc Output impedance misc Fully Random Rotation-based DEM
topic_browse	ddc 004 sdnb 37 rvk ZG 1100 bkl 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 misc Current Steering DAC misc Dynamic element matching misc Code dependent load variation misc Output impedance misc Fully Random Rotation-based DEM
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hierarchy_parent_title	International journal of electronics and communications
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title	A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
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title_full	A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
author_sort	Samanta, Smrutilekha
journal	International journal of electronics and communications
journalStr	International journal of electronics and communications
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author_browse	Samanta, Smrutilekha Sarkar, Santanu
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class	004 620 DE-600 37 621.3 sdnb ZG 1100 rvk 53.70 bkl 53.72 bkl 53.73 bkl 53.74 bkl 53.75 bkl 53.76 bkl
format_se	Elektronische Aufsätze
author-letter	Samanta, Smrutilekha
doi_str_mv	10.1016/j.aeue.2023.154528
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author2-role	verfasserin
title_sort	a 10-bit cs-dac using fully random rotation based dem and code independent output impedance compensation
title_auth	A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
abstract	This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.
abstractGer	This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.
abstract_unstemmed	This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm 2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.
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title_short	A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation
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doi_str	10.1016/j.aeue.2023.154528
up_date	2024-07-06T22:26:29.404Z
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A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

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