Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor
A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structur...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kao, Shao-Ku [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016transfer abstract |
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| Schlagwörter: |
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| Umfang: |
8 |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
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| Übergeordnetes Werk: |
volume:56 ; year:2016 ; pages:134-141 ; extent:8 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.mejo.2016.08.012 |
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| Katalog-ID: |
ELV019914520 |
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| 245 | 1 | 0 | |a Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor |
| 264 | 1 | |c 2016transfer abstract | |
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| 520 | |a A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. | ||
| 520 | |a A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. | ||
| 650 | 7 | |a Load transient response |2 Elsevier | |
| 650 | 7 | |a Dynamic biasing technique |2 Elsevier | |
| 650 | 7 | |a Slew-rate enhancement |2 Elsevier | |
| 650 | 7 | |a Low-dropout regulator |2 Elsevier | |
| 650 | 7 | |a Capacitive coupling |2 Elsevier | |
| 700 | 1 | |a Lee, Yu-Zhang |4 oth | |
| 700 | 1 | |a Ku, Chun-Yu |4 oth | |
| 700 | 1 | |a Cheng, Hsiang-Chi |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier Science |a Kokkinos, Peter ELSEVIER |t Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |d 2023 |g Amsterdam [u.a.] |w (DE-627)ELV009440992 |
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10.1016/j.mejo.2016.08.012 doi GBVA2016023000018.pica (DE-627)ELV019914520 (ELSEVIER)S0026-2692(16)30402-5 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor 2016transfer abstract 8 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. Load transient response Elsevier Dynamic biasing technique Elsevier Slew-rate enhancement Elsevier Low-dropout regulator Elsevier Capacitive coupling Elsevier Lee, Yu-Zhang oth Ku, Chun-Yu oth Cheng, Hsiang-Chi oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:56 year:2016 pages:134-141 extent:8 https://doi.org/10.1016/j.mejo.2016.08.012 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 56 2016 134-141 8 045F 620 |
| spelling |
10.1016/j.mejo.2016.08.012 doi GBVA2016023000018.pica (DE-627)ELV019914520 (ELSEVIER)S0026-2692(16)30402-5 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor 2016transfer abstract 8 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. Load transient response Elsevier Dynamic biasing technique Elsevier Slew-rate enhancement Elsevier Low-dropout regulator Elsevier Capacitive coupling Elsevier Lee, Yu-Zhang oth Ku, Chun-Yu oth Cheng, Hsiang-Chi oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:56 year:2016 pages:134-141 extent:8 https://doi.org/10.1016/j.mejo.2016.08.012 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 56 2016 134-141 8 045F 620 |
| allfields_unstemmed |
10.1016/j.mejo.2016.08.012 doi GBVA2016023000018.pica (DE-627)ELV019914520 (ELSEVIER)S0026-2692(16)30402-5 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor 2016transfer abstract 8 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. Load transient response Elsevier Dynamic biasing technique Elsevier Slew-rate enhancement Elsevier Low-dropout regulator Elsevier Capacitive coupling Elsevier Lee, Yu-Zhang oth Ku, Chun-Yu oth Cheng, Hsiang-Chi oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:56 year:2016 pages:134-141 extent:8 https://doi.org/10.1016/j.mejo.2016.08.012 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 56 2016 134-141 8 045F 620 |
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10.1016/j.mejo.2016.08.012 doi GBVA2016023000018.pica (DE-627)ELV019914520 (ELSEVIER)S0026-2692(16)30402-5 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor 2016transfer abstract 8 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. Load transient response Elsevier Dynamic biasing technique Elsevier Slew-rate enhancement Elsevier Low-dropout regulator Elsevier Capacitive coupling Elsevier Lee, Yu-Zhang oth Ku, Chun-Yu oth Cheng, Hsiang-Chi oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:56 year:2016 pages:134-141 extent:8 https://doi.org/10.1016/j.mejo.2016.08.012 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 56 2016 134-141 8 045F 620 |
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10.1016/j.mejo.2016.08.012 doi GBVA2016023000018.pica (DE-627)ELV019914520 (ELSEVIER)S0026-2692(16)30402-5 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor 2016transfer abstract 8 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. Load transient response Elsevier Dynamic biasing technique Elsevier Slew-rate enhancement Elsevier Low-dropout regulator Elsevier Capacitive coupling Elsevier Lee, Yu-Zhang oth Ku, Chun-Yu oth Cheng, Hsiang-Chi oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:56 year:2016 pages:134-141 extent:8 https://doi.org/10.1016/j.mejo.2016.08.012 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 56 2016 134-141 8 045F 620 |
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The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. 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Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor |
| abstract |
A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. |
| abstractGer |
A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. |
| abstract_unstemmed |
A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot. |
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Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor |
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