Drop-shock reliability improvement of embedded chip resistor packages through via structure modification
We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedde...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Park, Se-Hoon [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2016transfer abstract |
|---|
| Umfang: |
7 |
|---|
| Übergeordnetes Werk: |
Enthalten in: Fixed-time neural control for output-constrained synchronization of second-order chaotic systems - Yao, Qijia ELSEVIER, 2023, Amsterdam [u.a.] |
|---|---|
| Übergeordnetes Werk: |
volume:63 ; year:2016 ; pages:194-200 ; extent:7 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.microrel.2016.05.003 |
|---|
| Katalog-ID: |
ELV01991556X |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | ELV01991556X | ||
| 003 | DE-627 | ||
| 005 | 20230625130920.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 180603s2016 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1016/j.microrel.2016.05.003 |2 doi | |
| 028 | 5 | 2 | |a GBVA2016023000018.pica |
| 035 | |a (DE-627)ELV01991556X | ||
| 035 | |a (ELSEVIER)S0026-2714(16)30100-7 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | |a 620 | |
| 082 | 0 | 4 | |a 620 |q DE-600 |
| 082 | 0 | 4 | |a 510 |q VZ |
| 084 | |a 30.20 |2 bkl | ||
| 084 | |a 31.00 |2 bkl | ||
| 100 | 1 | |a Park, Se-Hoon |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| 264 | 1 | |c 2016transfer abstract | |
| 300 | |a 7 | ||
| 336 | |a nicht spezifiziert |b zzz |2 rdacontent | ||
| 337 | |a nicht spezifiziert |b z |2 rdamedia | ||
| 338 | |a nicht spezifiziert |b zu |2 rdacarrier | ||
| 520 | |a We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. | ||
| 520 | |a We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. | ||
| 700 | 1 | |a Park, Jong Chul |4 oth | |
| 700 | 1 | |a Park, Jae-Yong |4 oth | |
| 700 | 1 | |a Kim, Young-Ho |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier |a Yao, Qijia ELSEVIER |t Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |d 2023 |g Amsterdam [u.a.] |w (DE-627)ELV009442901 |
| 773 | 1 | 8 | |g volume:63 |g year:2016 |g pages:194-200 |g extent:7 |
| 856 | 4 | 0 | |u https://doi.org/10.1016/j.microrel.2016.05.003 |3 Volltext |
| 912 | |a GBV_USEFLAG_U | ||
| 912 | |a GBV_ELV | ||
| 912 | |a SYSFLAG_U | ||
| 912 | |a SSG-OPC-MAT | ||
| 936 | b | k | |a 30.20 |j Nichtlineare Dynamik |q VZ |
| 936 | b | k | |a 31.00 |j Mathematik: Allgemeines |q VZ |
| 951 | |a AR | ||
| 952 | |d 63 |j 2016 |h 194-200 |g 7 | ||
| 953 | |2 045F |a 620 | ||
| author_variant |
s h p shp |
|---|---|
| matchkey_str |
parksehoonparkjongchulparkjaeyongkimyoun:2016----:rphcrlaiiymrvmnoebdecirssopcaetruh |
| hierarchy_sort_str |
2016transfer abstract |
| bklnumber |
30.20 31.00 |
| publishDate |
2016 |
| allfields |
10.1016/j.microrel.2016.05.003 doi GBVA2016023000018.pica (DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Park, Se-Hoon verfasserin aut Drop-shock reliability improvement of embedded chip resistor packages through via structure modification 2016transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. Park, Jong Chul oth Park, Jae-Yong oth Kim, Young-Ho oth Enthalten in Elsevier Yao, Qijia ELSEVIER Fixed-time neural control for output-constrained synchronization of second-order chaotic systems 2023 Amsterdam [u.a.] (DE-627)ELV009442901 volume:63 year:2016 pages:194-200 extent:7 https://doi.org/10.1016/j.microrel.2016.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT 30.20 Nichtlineare Dynamik VZ 31.00 Mathematik: Allgemeines VZ AR 63 2016 194-200 7 045F 620 |
| spelling |
10.1016/j.microrel.2016.05.003 doi GBVA2016023000018.pica (DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Park, Se-Hoon verfasserin aut Drop-shock reliability improvement of embedded chip resistor packages through via structure modification 2016transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. Park, Jong Chul oth Park, Jae-Yong oth Kim, Young-Ho oth Enthalten in Elsevier Yao, Qijia ELSEVIER Fixed-time neural control for output-constrained synchronization of second-order chaotic systems 2023 Amsterdam [u.a.] (DE-627)ELV009442901 volume:63 year:2016 pages:194-200 extent:7 https://doi.org/10.1016/j.microrel.2016.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT 30.20 Nichtlineare Dynamik VZ 31.00 Mathematik: Allgemeines VZ AR 63 2016 194-200 7 045F 620 |
| allfields_unstemmed |
10.1016/j.microrel.2016.05.003 doi GBVA2016023000018.pica (DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Park, Se-Hoon verfasserin aut Drop-shock reliability improvement of embedded chip resistor packages through via structure modification 2016transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. Park, Jong Chul oth Park, Jae-Yong oth Kim, Young-Ho oth Enthalten in Elsevier Yao, Qijia ELSEVIER Fixed-time neural control for output-constrained synchronization of second-order chaotic systems 2023 Amsterdam [u.a.] (DE-627)ELV009442901 volume:63 year:2016 pages:194-200 extent:7 https://doi.org/10.1016/j.microrel.2016.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT 30.20 Nichtlineare Dynamik VZ 31.00 Mathematik: Allgemeines VZ AR 63 2016 194-200 7 045F 620 |
| allfieldsGer |
10.1016/j.microrel.2016.05.003 doi GBVA2016023000018.pica (DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Park, Se-Hoon verfasserin aut Drop-shock reliability improvement of embedded chip resistor packages through via structure modification 2016transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. Park, Jong Chul oth Park, Jae-Yong oth Kim, Young-Ho oth Enthalten in Elsevier Yao, Qijia ELSEVIER Fixed-time neural control for output-constrained synchronization of second-order chaotic systems 2023 Amsterdam [u.a.] (DE-627)ELV009442901 volume:63 year:2016 pages:194-200 extent:7 https://doi.org/10.1016/j.microrel.2016.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT 30.20 Nichtlineare Dynamik VZ 31.00 Mathematik: Allgemeines VZ AR 63 2016 194-200 7 045F 620 |
| allfieldsSound |
10.1016/j.microrel.2016.05.003 doi GBVA2016023000018.pica (DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Park, Se-Hoon verfasserin aut Drop-shock reliability improvement of embedded chip resistor packages through via structure modification 2016transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. Park, Jong Chul oth Park, Jae-Yong oth Kim, Young-Ho oth Enthalten in Elsevier Yao, Qijia ELSEVIER Fixed-time neural control for output-constrained synchronization of second-order chaotic systems 2023 Amsterdam [u.a.] (DE-627)ELV009442901 volume:63 year:2016 pages:194-200 extent:7 https://doi.org/10.1016/j.microrel.2016.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT 30.20 Nichtlineare Dynamik VZ 31.00 Mathematik: Allgemeines VZ AR 63 2016 194-200 7 045F 620 |
| language |
English |
| source |
Enthalten in Fixed-time neural control for output-constrained synchronization of second-order chaotic systems Amsterdam [u.a.] volume:63 year:2016 pages:194-200 extent:7 |
| sourceStr |
Enthalten in Fixed-time neural control for output-constrained synchronization of second-order chaotic systems Amsterdam [u.a.] volume:63 year:2016 pages:194-200 extent:7 |
| format_phy_str_mv |
Article |
| bklname |
Nichtlineare Dynamik Mathematik: Allgemeines |
| institution |
findex.gbv.de |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |
| authorswithroles_txt_mv |
Park, Se-Hoon @@aut@@ Park, Jong Chul @@oth@@ Park, Jae-Yong @@oth@@ Kim, Young-Ho @@oth@@ |
| publishDateDaySort_date |
2016-01-01T00:00:00Z |
| hierarchy_top_id |
ELV009442901 |
| dewey-sort |
3620 |
| id |
ELV01991556X |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV01991556X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625130920.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2016 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.microrel.2016.05.003</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2016023000018.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV01991556X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0026-2714(16)30100-7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">510</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">30.20</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">31.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Park, Se-Hoon</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Drop-shock reliability improvement of embedded chip resistor packages through via structure modification</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">7</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Park, Jong Chul</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Park, Jae-Yong</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Young-Ho</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier</subfield><subfield code="a">Yao, Qijia ELSEVIER</subfield><subfield code="t">Fixed-time neural control for output-constrained synchronization of second-order chaotic systems</subfield><subfield code="d">2023</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV009442901</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:63</subfield><subfield code="g">year:2016</subfield><subfield code="g">pages:194-200</subfield><subfield code="g">extent:7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.microrel.2016.05.003</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-MAT</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">30.20</subfield><subfield code="j">Nichtlineare Dynamik</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">31.00</subfield><subfield code="j">Mathematik: Allgemeines</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">63</subfield><subfield code="j">2016</subfield><subfield code="h">194-200</subfield><subfield code="g">7</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">620</subfield></datafield></record></collection>
|
| author |
Park, Se-Hoon |
| spellingShingle |
Park, Se-Hoon ddc 620 ddc 510 bkl 30.20 bkl 31.00 Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| authorStr |
Park, Se-Hoon |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)ELV009442901 |
| format |
electronic Article |
| dewey-ones |
620 - Engineering & allied operations 510 - Mathematics |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
elsevier |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| topic |
ddc 620 ddc 510 bkl 30.20 bkl 31.00 |
| topic_unstemmed |
ddc 620 ddc 510 bkl 30.20 bkl 31.00 |
| topic_browse |
ddc 620 ddc 510 bkl 30.20 bkl 31.00 |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
zu |
| author2_variant |
j c p jc jcp j y p jyp y h k yhk |
| hierarchy_parent_title |
Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |
| hierarchy_parent_id |
ELV009442901 |
| dewey-tens |
620 - Engineering 510 - Mathematics |
| hierarchy_top_title |
Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)ELV009442901 |
| title |
Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| ctrlnum |
(DE-627)ELV01991556X (ELSEVIER)S0026-2714(16)30100-7 |
| title_full |
Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| author_sort |
Park, Se-Hoon |
| journal |
Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |
| journalStr |
Fixed-time neural control for output-constrained synchronization of second-order chaotic systems |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology 500 - Science |
| recordtype |
marc |
| publishDateSort |
2016 |
| contenttype_str_mv |
zzz |
| container_start_page |
194 |
| author_browse |
Park, Se-Hoon |
| container_volume |
63 |
| physical |
7 |
| class |
620 620 DE-600 510 VZ 30.20 bkl 31.00 bkl |
| format_se |
Elektronische Aufsätze |
| author-letter |
Park, Se-Hoon |
| doi_str_mv |
10.1016/j.microrel.2016.05.003 |
| dewey-full |
620 510 |
| title_sort |
drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| title_auth |
Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| abstract |
We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. |
| abstractGer |
We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. |
| abstract_unstemmed |
We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. |
| collection_details |
GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-MAT |
| title_short |
Drop-shock reliability improvement of embedded chip resistor packages through via structure modification |
| url |
https://doi.org/10.1016/j.microrel.2016.05.003 |
| remote_bool |
true |
| author2 |
Park, Jong Chul Park, Jae-Yong Kim, Young-Ho |
| author2Str |
Park, Jong Chul Park, Jae-Yong Kim, Young-Ho |
| ppnlink |
ELV009442901 |
| mediatype_str_mv |
z |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth oth |
| doi_str |
10.1016/j.microrel.2016.05.003 |
| up_date |
2024-07-06T22:42:59.515Z |
| _version_ |
1803871353061769216 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV01991556X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625130920.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2016 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.microrel.2016.05.003</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2016023000018.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV01991556X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0026-2714(16)30100-7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">510</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">30.20</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">31.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Park, Se-Hoon</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Drop-shock reliability improvement of embedded chip resistor packages through via structure modification</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">7</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Park, Jong Chul</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Park, Jae-Yong</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Young-Ho</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier</subfield><subfield code="a">Yao, Qijia ELSEVIER</subfield><subfield code="t">Fixed-time neural control for output-constrained synchronization of second-order chaotic systems</subfield><subfield code="d">2023</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV009442901</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:63</subfield><subfield code="g">year:2016</subfield><subfield code="g">pages:194-200</subfield><subfield code="g">extent:7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.microrel.2016.05.003</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-MAT</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">30.20</subfield><subfield code="j">Nichtlineare Dynamik</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">31.00</subfield><subfield code="j">Mathematik: Allgemeines</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">63</subfield><subfield code="j">2016</subfield><subfield code="h">194-200</subfield><subfield code="g">7</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">620</subfield></datafield></record></collection>
|
| score |
7.3972692 |