Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces
The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional v...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Van Rethy, Jelle [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2014transfer abstract |
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| Schlagwörter: |
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| Umfang: |
7 |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
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| Übergeordnetes Werk: |
volume:45 ; year:2014 ; number:12 ; pages:1641-1647 ; extent:7 |
| Links: |
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| DOI / URN: |
10.1016/j.mejo.2014.06.007 |
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ELV023150653 |
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| 520 | |a The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. | ||
| 520 | |a The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. | ||
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10.1016/j.mejo.2014.06.007 doi GBVA2014022000013.pica (DE-627)ELV023150653 (ELSEVIER)S0026-2692(14)00206-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Van Rethy, Jelle verfasserin aut Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. BBPLL Elsevier Sensor interface Elsevier Time/frequency-based Elsevier Danneels, Hans oth Gielen, Georges oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:12 pages:1641-1647 extent:7 https://doi.org/10.1016/j.mejo.2014.06.007 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 12 1641-1647 7 045F 620 |
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10.1016/j.mejo.2014.06.007 doi GBVA2014022000013.pica (DE-627)ELV023150653 (ELSEVIER)S0026-2692(14)00206-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Van Rethy, Jelle verfasserin aut Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. BBPLL Elsevier Sensor interface Elsevier Time/frequency-based Elsevier Danneels, Hans oth Gielen, Georges oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:12 pages:1641-1647 extent:7 https://doi.org/10.1016/j.mejo.2014.06.007 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 12 1641-1647 7 045F 620 |
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10.1016/j.mejo.2014.06.007 doi GBVA2014022000013.pica (DE-627)ELV023150653 (ELSEVIER)S0026-2692(14)00206-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Van Rethy, Jelle verfasserin aut Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. BBPLL Elsevier Sensor interface Elsevier Time/frequency-based Elsevier Danneels, Hans oth Gielen, Georges oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:12 pages:1641-1647 extent:7 https://doi.org/10.1016/j.mejo.2014.06.007 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 12 1641-1647 7 045F 620 |
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10.1016/j.mejo.2014.06.007 doi GBVA2014022000013.pica (DE-627)ELV023150653 (ELSEVIER)S0026-2692(14)00206-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Van Rethy, Jelle verfasserin aut Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. BBPLL Elsevier Sensor interface Elsevier Time/frequency-based Elsevier Danneels, Hans oth Gielen, Georges oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:12 pages:1641-1647 extent:7 https://doi.org/10.1016/j.mejo.2014.06.007 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 12 1641-1647 7 045F 620 |
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10.1016/j.mejo.2014.06.007 doi GBVA2014022000013.pica (DE-627)ELV023150653 (ELSEVIER)S0026-2692(14)00206-7 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Van Rethy, Jelle verfasserin aut Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. BBPLL Elsevier Sensor interface Elsevier Time/frequency-based Elsevier Danneels, Hans oth Gielen, Georges oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:12 pages:1641-1647 extent:7 https://doi.org/10.1016/j.mejo.2014.06.007 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 12 1641-1647 7 045F 620 |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces |
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Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces |
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Van Rethy, Jelle |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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scalable bang–bang phase-locked-loop-based integrated sensor interfaces |
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Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces |
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The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. |
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The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. |
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The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect. |
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Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces |
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https://doi.org/10.1016/j.mejo.2014.06.007 |
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Danneels, Hans Gielen, Georges |
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