Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios
Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Nanda, Umakanta [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017transfer abstract |
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| Schlagwörter: |
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| Umfang: |
7 |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
|---|---|
| Übergeordnetes Werk: |
volume:64 ; year:2017 ; pages:92-98 ; extent:7 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.mejo.2017.04.011 |
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ELV025674935 |
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| 520 | |a Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. | ||
| 520 | |a Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. | ||
| 650 | 7 | |a Fast lock in time |2 Elsevier | |
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10.1016/j.mejo.2017.04.011 doi GBVA2017022000013.pica (DE-627)ELV025674935 (ELSEVIER)S0026-2692(16)30603-6 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Nanda, Umakanta verfasserin aut Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios 2017transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier Acharya, Debiprasad Priyabrata oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:64 year:2017 pages:92-98 extent:7 https://doi.org/10.1016/j.mejo.2017.04.011 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 64 2017 92-98 7 045F 620 |
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10.1016/j.mejo.2017.04.011 doi GBVA2017022000013.pica (DE-627)ELV025674935 (ELSEVIER)S0026-2692(16)30603-6 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Nanda, Umakanta verfasserin aut Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios 2017transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier Acharya, Debiprasad Priyabrata oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:64 year:2017 pages:92-98 extent:7 https://doi.org/10.1016/j.mejo.2017.04.011 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 64 2017 92-98 7 045F 620 |
| allfields_unstemmed |
10.1016/j.mejo.2017.04.011 doi GBVA2017022000013.pica (DE-627)ELV025674935 (ELSEVIER)S0026-2692(16)30603-6 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Nanda, Umakanta verfasserin aut Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios 2017transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier Acharya, Debiprasad Priyabrata oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:64 year:2017 pages:92-98 extent:7 https://doi.org/10.1016/j.mejo.2017.04.011 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 64 2017 92-98 7 045F 620 |
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10.1016/j.mejo.2017.04.011 doi GBVA2017022000013.pica (DE-627)ELV025674935 (ELSEVIER)S0026-2692(16)30603-6 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Nanda, Umakanta verfasserin aut Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios 2017transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier Acharya, Debiprasad Priyabrata oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:64 year:2017 pages:92-98 extent:7 https://doi.org/10.1016/j.mejo.2017.04.011 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 64 2017 92-98 7 045F 620 |
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10.1016/j.mejo.2017.04.011 doi GBVA2017022000013.pica (DE-627)ELV025674935 (ELSEVIER)S0026-2692(16)30603-6 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Nanda, Umakanta verfasserin aut Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios 2017transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier Acharya, Debiprasad Priyabrata oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:64 year:2017 pages:92-98 extent:7 https://doi.org/10.1016/j.mejo.2017.04.011 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 64 2017 92-98 7 045F 620 |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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620 620 DE-600 610 VZ 44.85 bkl Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios Fast lock in time Elsevier Low jitter Elsevier Adaptive PFD selector Elsevier Phase locked loop Elsevier Low phase noise Elsevier |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios |
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Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios |
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Nanda, Umakanta |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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Nanda, Umakanta |
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10.1016/j.mejo.2017.04.011 |
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adaptive pfd selection technique for low noise and fast pll in multi-standard radios |
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Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios |
| abstract |
Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. |
| abstractGer |
Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. |
| abstract_unstemmed |
Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX. |
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Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios |
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Acharya, Debiprasad Priyabrata |
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