Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling
Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system u...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Mishra, Abhishek [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2014transfer abstract |
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| Schlagwörter: |
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| Umfang: |
11 |
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| Übergeordnetes Werk: |
Enthalten in: Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume - Srivastava, Rajesh K. ELSEVIER, 2022, simulation and computation for engineering and environmental systems, Amsterdam [u.a.] |
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| Übergeordnetes Werk: |
volume:38 ; year:2014 ; number:14 ; day:15 ; month:07 ; pages:3456-3466 ; extent:11 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.apm.2013.12.009 |
|---|
| Katalog-ID: |
ELV028070135 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | ELV028070135 | ||
| 003 | DE-627 | ||
| 005 | 20230625152924.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 180603s2014 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1016/j.apm.2013.12.009 |2 doi | |
| 028 | 5 | 2 | |a GBVA2014009000022.pica |
| 035 | |a (DE-627)ELV028070135 | ||
| 035 | |a (ELSEVIER)S0307-904X(13)00814-7 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | |a 510 | |
| 082 | 0 | 4 | |a 510 |q DE-600 |
| 082 | 0 | 4 | |a 550 |q VZ |
| 084 | |a 38.00 |2 bkl | ||
| 100 | 1 | |a Mishra, Abhishek |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| 264 | 1 | |c 2014transfer abstract | |
| 300 | |a 11 | ||
| 336 | |a nicht spezifiziert |b zzz |2 rdacontent | ||
| 337 | |a nicht spezifiziert |b z |2 rdamedia | ||
| 338 | |a nicht spezifiziert |b zu |2 rdacarrier | ||
| 520 | |a Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. | ||
| 520 | |a Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. | ||
| 650 | 7 | |a Multi-core processors |2 Elsevier | |
| 650 | 7 | |a Integer linear programming |2 Elsevier | |
| 650 | 7 | |a Energy efficient scheduling |2 Elsevier | |
| 650 | 7 | |a Dynamic voltage scaling |2 Elsevier | |
| 700 | 1 | |a Tripathi, Anil Kumar |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier Science |a Srivastava, Rajesh K. ELSEVIER |t Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |d 2022 |d simulation and computation for engineering and environmental systems |g Amsterdam [u.a.] |w (DE-627)ELV008859868 |
| 773 | 1 | 8 | |g volume:38 |g year:2014 |g number:14 |g day:15 |g month:07 |g pages:3456-3466 |g extent:11 |
| 856 | 4 | 0 | |u https://doi.org/10.1016/j.apm.2013.12.009 |3 Volltext |
| 912 | |a GBV_USEFLAG_U | ||
| 912 | |a GBV_ELV | ||
| 912 | |a SYSFLAG_U | ||
| 912 | |a SSG-OPC-GGO | ||
| 936 | b | k | |a 38.00 |j Geowissenschaften: Allgemeines |q VZ |
| 951 | |a AR | ||
| 952 | |d 38 |j 2014 |e 14 |b 15 |c 0715 |h 3456-3466 |g 11 | ||
| 953 | |2 045F |a 510 | ||
| author_variant |
a m am |
|---|---|
| matchkey_str |
mishraabhishektripathianilkumar:2014----:nryfiinvlaeceuigomlioercsosihotaeoto |
| hierarchy_sort_str |
2014transfer abstract |
| bklnumber |
38.00 |
| publishDate |
2014 |
| allfields |
10.1016/j.apm.2013.12.009 doi GBVA2014009000022.pica (DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 DE-627 ger DE-627 rakwb eng 510 510 DE-600 550 VZ 38.00 bkl Mishra, Abhishek verfasserin aut Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling 2014transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier Tripathi, Anil Kumar oth Enthalten in Elsevier Science Srivastava, Rajesh K. ELSEVIER Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume 2022 simulation and computation for engineering and environmental systems Amsterdam [u.a.] (DE-627)ELV008859868 volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 https://doi.org/10.1016/j.apm.2013.12.009 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO 38.00 Geowissenschaften: Allgemeines VZ AR 38 2014 14 15 0715 3456-3466 11 045F 510 |
| spelling |
10.1016/j.apm.2013.12.009 doi GBVA2014009000022.pica (DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 DE-627 ger DE-627 rakwb eng 510 510 DE-600 550 VZ 38.00 bkl Mishra, Abhishek verfasserin aut Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling 2014transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier Tripathi, Anil Kumar oth Enthalten in Elsevier Science Srivastava, Rajesh K. ELSEVIER Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume 2022 simulation and computation for engineering and environmental systems Amsterdam [u.a.] (DE-627)ELV008859868 volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 https://doi.org/10.1016/j.apm.2013.12.009 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO 38.00 Geowissenschaften: Allgemeines VZ AR 38 2014 14 15 0715 3456-3466 11 045F 510 |
| allfields_unstemmed |
10.1016/j.apm.2013.12.009 doi GBVA2014009000022.pica (DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 DE-627 ger DE-627 rakwb eng 510 510 DE-600 550 VZ 38.00 bkl Mishra, Abhishek verfasserin aut Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling 2014transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier Tripathi, Anil Kumar oth Enthalten in Elsevier Science Srivastava, Rajesh K. ELSEVIER Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume 2022 simulation and computation for engineering and environmental systems Amsterdam [u.a.] (DE-627)ELV008859868 volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 https://doi.org/10.1016/j.apm.2013.12.009 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO 38.00 Geowissenschaften: Allgemeines VZ AR 38 2014 14 15 0715 3456-3466 11 045F 510 |
| allfieldsGer |
10.1016/j.apm.2013.12.009 doi GBVA2014009000022.pica (DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 DE-627 ger DE-627 rakwb eng 510 510 DE-600 550 VZ 38.00 bkl Mishra, Abhishek verfasserin aut Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling 2014transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier Tripathi, Anil Kumar oth Enthalten in Elsevier Science Srivastava, Rajesh K. ELSEVIER Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume 2022 simulation and computation for engineering and environmental systems Amsterdam [u.a.] (DE-627)ELV008859868 volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 https://doi.org/10.1016/j.apm.2013.12.009 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO 38.00 Geowissenschaften: Allgemeines VZ AR 38 2014 14 15 0715 3456-3466 11 045F 510 |
| allfieldsSound |
10.1016/j.apm.2013.12.009 doi GBVA2014009000022.pica (DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 DE-627 ger DE-627 rakwb eng 510 510 DE-600 550 VZ 38.00 bkl Mishra, Abhishek verfasserin aut Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling 2014transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier Tripathi, Anil Kumar oth Enthalten in Elsevier Science Srivastava, Rajesh K. ELSEVIER Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume 2022 simulation and computation for engineering and environmental systems Amsterdam [u.a.] (DE-627)ELV008859868 volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 https://doi.org/10.1016/j.apm.2013.12.009 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO 38.00 Geowissenschaften: Allgemeines VZ AR 38 2014 14 15 0715 3456-3466 11 045F 510 |
| language |
English |
| source |
Enthalten in Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume Amsterdam [u.a.] volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 |
| sourceStr |
Enthalten in Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume Amsterdam [u.a.] volume:38 year:2014 number:14 day:15 month:07 pages:3456-3466 extent:11 |
| format_phy_str_mv |
Article |
| bklname |
Geowissenschaften: Allgemeines |
| institution |
findex.gbv.de |
| topic_facet |
Multi-core processors Integer linear programming Energy efficient scheduling Dynamic voltage scaling |
| dewey-raw |
510 |
| isfreeaccess_bool |
false |
| container_title |
Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |
| authorswithroles_txt_mv |
Mishra, Abhishek @@aut@@ Tripathi, Anil Kumar @@oth@@ |
| publishDateDaySort_date |
2014-01-15T00:00:00Z |
| hierarchy_top_id |
ELV008859868 |
| dewey-sort |
3510 |
| id |
ELV028070135 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV028070135</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625152924.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2014 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.apm.2013.12.009</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2014009000022.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV028070135</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0307-904X(13)00814-7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">510</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">510</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">550</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">38.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Mishra, Abhishek</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2014transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">11</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Multi-core processors</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integer linear programming</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Energy efficient scheduling</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Dynamic voltage scaling</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Tripathi, Anil Kumar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier Science</subfield><subfield code="a">Srivastava, Rajesh K. ELSEVIER</subfield><subfield code="t">Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume</subfield><subfield code="d">2022</subfield><subfield code="d">simulation and computation for engineering and environmental systems</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV008859868</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:38</subfield><subfield code="g">year:2014</subfield><subfield code="g">number:14</subfield><subfield code="g">day:15</subfield><subfield code="g">month:07</subfield><subfield code="g">pages:3456-3466</subfield><subfield code="g">extent:11</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.apm.2013.12.009</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-GGO</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">38.00</subfield><subfield code="j">Geowissenschaften: Allgemeines</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">38</subfield><subfield code="j">2014</subfield><subfield code="e">14</subfield><subfield code="b">15</subfield><subfield code="c">0715</subfield><subfield code="h">3456-3466</subfield><subfield code="g">11</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">510</subfield></datafield></record></collection>
|
| author |
Mishra, Abhishek |
| spellingShingle |
Mishra, Abhishek ddc 510 ddc 550 bkl 38.00 Elsevier Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| authorStr |
Mishra, Abhishek |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)ELV008859868 |
| format |
electronic Article |
| dewey-ones |
510 - Mathematics 550 - Earth sciences |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
elsevier |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
510 510 DE-600 550 VZ 38.00 bkl Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling Elsevier |
| topic |
ddc 510 ddc 550 bkl 38.00 Elsevier Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling |
| topic_unstemmed |
ddc 510 ddc 550 bkl 38.00 Elsevier Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling |
| topic_browse |
ddc 510 ddc 550 bkl 38.00 Elsevier Multi-core processors Elsevier Integer linear programming Elsevier Energy efficient scheduling Elsevier Dynamic voltage scaling |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
zu |
| author2_variant |
a k t ak akt |
| hierarchy_parent_title |
Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |
| hierarchy_parent_id |
ELV008859868 |
| dewey-tens |
510 - Mathematics 550 - Earth sciences & geology |
| hierarchy_top_title |
Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)ELV008859868 |
| title |
Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| ctrlnum |
(DE-627)ELV028070135 (ELSEVIER)S0307-904X(13)00814-7 |
| title_full |
Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| author_sort |
Mishra, Abhishek |
| journal |
Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |
| journalStr |
Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
500 - Science |
| recordtype |
marc |
| publishDateSort |
2014 |
| contenttype_str_mv |
zzz |
| container_start_page |
3456 |
| author_browse |
Mishra, Abhishek |
| container_volume |
38 |
| physical |
11 |
| class |
510 510 DE-600 550 VZ 38.00 bkl |
| format_se |
Elektronische Aufsätze |
| author-letter |
Mishra, Abhishek |
| doi_str_mv |
10.1016/j.apm.2013.12.009 |
| dewey-full |
510 550 |
| title_sort |
energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| title_auth |
Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| abstract |
Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. |
| abstractGer |
Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. |
| abstract_unstemmed |
Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants. |
| collection_details |
GBV_USEFLAG_U GBV_ELV SYSFLAG_U SSG-OPC-GGO |
| container_issue |
14 |
| title_short |
Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling |
| url |
https://doi.org/10.1016/j.apm.2013.12.009 |
| remote_bool |
true |
| author2 |
Tripathi, Anil Kumar |
| author2Str |
Tripathi, Anil Kumar |
| ppnlink |
ELV008859868 |
| mediatype_str_mv |
z |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth |
| doi_str |
10.1016/j.apm.2013.12.009 |
| up_date |
2024-07-06T17:51:51.936Z |
| _version_ |
1803853036978700288 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV028070135</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625152924.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2014 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.apm.2013.12.009</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2014009000022.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV028070135</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0307-904X(13)00814-7</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">510</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">510</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">550</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">38.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Mishra, Abhishek</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2014transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">11</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Energy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem. Through a series of reductions we reduce the IP formulation of the problem into an Integer Linear Program (ILP) formulation and prove that the proposed IP for the problem can be solved in O ( D ( log ( max ( s max , p ) + 1 ) + qlog ( Dp + 1 ) ) + log ( α ps max 3 D ) ( 2 q ( 4 q + 3 ) log ( max ( Dp , C ) + 2 ) ) a 2 q ) time where D is the given deadline, C is the amount of computation that has to be completed within the deadline of D time units, p is the number of cores, q is the number of possible core speeds, s max is the maximum speed of cores, and α and a are constants.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Multi-core processors</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integer linear programming</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Energy efficient scheduling</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Dynamic voltage scaling</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Tripathi, Anil Kumar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier Science</subfield><subfield code="a">Srivastava, Rajesh K. ELSEVIER</subfield><subfield code="t">Early Cretaceous mafic dykes from the Chhota Nagpur Gneissic Terrane, eastern India: Evidence of multiple magma pulses for the main stage of the Greater Kerguelen mantle plume</subfield><subfield code="d">2022</subfield><subfield code="d">simulation and computation for engineering and environmental systems</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV008859868</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:38</subfield><subfield code="g">year:2014</subfield><subfield code="g">number:14</subfield><subfield code="g">day:15</subfield><subfield code="g">month:07</subfield><subfield code="g">pages:3456-3466</subfield><subfield code="g">extent:11</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.apm.2013.12.009</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-GGO</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">38.00</subfield><subfield code="j">Geowissenschaften: Allgemeines</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">38</subfield><subfield code="j">2014</subfield><subfield code="e">14</subfield><subfield code="b">15</subfield><subfield code="c">0715</subfield><subfield code="h">3456-3466</subfield><subfield code="g">11</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">510</subfield></datafield></record></collection>
|
| score |
7.4001293 |