Frequency presetting and phase error detection technique for fast-locking phase-locked loop
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the contro...
Ausführliche Beschreibung
Autor*in: |
Kao, Shao-Ku [verfasserIn] |
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Format: |
E-Artikel |
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Sprache: |
Englisch |
Erschienen: |
2014transfer abstract |
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Umfang: |
7 |
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Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
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Übergeordnetes Werk: |
volume:45 ; year:2014 ; number:4 ; pages:375-381 ; extent:7 |
Links: |
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DOI / URN: |
10.1016/j.mejo.2014.01.003 |
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Katalog-ID: |
ELV034249508 |
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520 | |a A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. | ||
520 | |a A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. | ||
650 | 7 | |a Phase error detector |2 Elsevier | |
650 | 7 | |a Phase-locked loop |2 Elsevier | |
650 | 7 | |a Fast-lock |2 Elsevier | |
650 | 7 | |a Frequency tracking |2 Elsevier | |
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10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
spelling |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
allfields_unstemmed |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
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10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
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10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
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A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
abstractGer |
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
abstract_unstemmed |
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
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title_short |
Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
url |
https://doi.org/10.1016/j.mejo.2014.01.003 |
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doi_str |
10.1016/j.mejo.2014.01.003 |
up_date |
2024-07-06T20:38:29.582Z |
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