Frequency presetting and phase error detection technique for fast-locking phase-locked loop
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the contro...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kao, Shao-Ku [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2014transfer abstract |
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| Schlagwörter: |
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| Umfang: |
7 |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
|---|---|
| Übergeordnetes Werk: |
volume:45 ; year:2014 ; number:4 ; pages:375-381 ; extent:7 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.mejo.2014.01.003 |
|---|
| Katalog-ID: |
ELV034249508 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | ELV034249508 | ||
| 003 | DE-627 | ||
| 005 | 20230625200332.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 180603s2014 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1016/j.mejo.2014.01.003 |2 doi | |
| 028 | 5 | 2 | |a GBVA2014022000012.pica |
| 035 | |a (DE-627)ELV034249508 | ||
| 035 | |a (ELSEVIER)S0026-2692(14)00004-4 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | |a 620 | |
| 082 | 0 | 4 | |a 620 |q DE-600 |
| 082 | 0 | 4 | |a 610 |q VZ |
| 084 | |a 44.85 |2 bkl | ||
| 100 | 1 | |a Kao, Shao-Ku |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| 264 | 1 | |c 2014transfer abstract | |
| 300 | |a 7 | ||
| 336 | |a nicht spezifiziert |b zzz |2 rdacontent | ||
| 337 | |a nicht spezifiziert |b z |2 rdamedia | ||
| 338 | |a nicht spezifiziert |b zu |2 rdacarrier | ||
| 520 | |a A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. | ||
| 520 | |a A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. | ||
| 650 | 7 | |a Phase error detector |2 Elsevier | |
| 650 | 7 | |a Phase-locked loop |2 Elsevier | |
| 650 | 7 | |a Fast-lock |2 Elsevier | |
| 650 | 7 | |a Frequency tracking |2 Elsevier | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier Science |a Kokkinos, Peter ELSEVIER |t Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |d 2023 |g Amsterdam [u.a.] |w (DE-627)ELV009440992 |
| 773 | 1 | 8 | |g volume:45 |g year:2014 |g number:4 |g pages:375-381 |g extent:7 |
| 856 | 4 | 0 | |u https://doi.org/10.1016/j.mejo.2014.01.003 |3 Volltext |
| 912 | |a GBV_USEFLAG_U | ||
| 912 | |a GBV_ELV | ||
| 912 | |a SYSFLAG_U | ||
| 936 | b | k | |a 44.85 |j Kardiologie |j Angiologie |q VZ |
| 951 | |a AR | ||
| 952 | |d 45 |j 2014 |e 4 |h 375-381 |g 7 | ||
| 953 | |2 045F |a 620 | ||
| author_variant |
s k k skk |
|---|---|
| matchkey_str |
kaoshaoku:2014----:rqecpeetnadhserreetotcnqeofs |
| hierarchy_sort_str |
2014transfer abstract |
| bklnumber |
44.85 |
| publishDate |
2014 |
| allfields |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
| spelling |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
| allfields_unstemmed |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
| allfieldsGer |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
| allfieldsSound |
10.1016/j.mejo.2014.01.003 doi GBVA2014022000012.pica (DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Kao, Shao-Ku verfasserin aut Frequency presetting and phase error detection technique for fast-locking phase-locked loop 2014transfer abstract 7 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:45 year:2014 number:4 pages:375-381 extent:7 https://doi.org/10.1016/j.mejo.2014.01.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 45 2014 4 375-381 7 045F 620 |
| language |
English |
| source |
Enthalten in Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease Amsterdam [u.a.] volume:45 year:2014 number:4 pages:375-381 extent:7 |
| sourceStr |
Enthalten in Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease Amsterdam [u.a.] volume:45 year:2014 number:4 pages:375-381 extent:7 |
| format_phy_str_mv |
Article |
| bklname |
Kardiologie Angiologie |
| institution |
findex.gbv.de |
| topic_facet |
Phase error detector Phase-locked loop Fast-lock Frequency tracking |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
| authorswithroles_txt_mv |
Kao, Shao-Ku @@aut@@ |
| publishDateDaySort_date |
2014-01-01T00:00:00Z |
| hierarchy_top_id |
ELV009440992 |
| dewey-sort |
3620 |
| id |
ELV034249508 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV034249508</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625200332.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2014 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.mejo.2014.01.003</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2014022000012.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV034249508</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0026-2692(14)00004-4</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">610</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">44.85</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kao, Shao-Ku</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Frequency presetting and phase error detection technique for fast-locking phase-locked loop</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2014transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">7</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Phase error detector</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Phase-locked loop</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Fast-lock</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Frequency tracking</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier Science</subfield><subfield code="a">Kokkinos, Peter ELSEVIER</subfield><subfield code="t">Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease</subfield><subfield code="d">2023</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV009440992</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:45</subfield><subfield code="g">year:2014</subfield><subfield code="g">number:4</subfield><subfield code="g">pages:375-381</subfield><subfield code="g">extent:7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.mejo.2014.01.003</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">44.85</subfield><subfield code="j">Kardiologie</subfield><subfield code="j">Angiologie</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">45</subfield><subfield code="j">2014</subfield><subfield code="e">4</subfield><subfield code="h">375-381</subfield><subfield code="g">7</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">620</subfield></datafield></record></collection>
|
| author |
Kao, Shao-Ku |
| spellingShingle |
Kao, Shao-Ku ddc 620 ddc 610 bkl 44.85 Elsevier Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| authorStr |
Kao, Shao-Ku |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)ELV009440992 |
| format |
electronic Article |
| dewey-ones |
620 - Engineering & allied operations 610 - Medicine & health |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
elsevier |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
620 620 DE-600 610 VZ 44.85 bkl Frequency presetting and phase error detection technique for fast-locking phase-locked loop Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking Elsevier |
| topic |
ddc 620 ddc 610 bkl 44.85 Elsevier Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking |
| topic_unstemmed |
ddc 620 ddc 610 bkl 44.85 Elsevier Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking |
| topic_browse |
ddc 620 ddc 610 bkl 44.85 Elsevier Phase error detector Elsevier Phase-locked loop Elsevier Fast-lock Elsevier Frequency tracking |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
zu |
| hierarchy_parent_title |
Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
| hierarchy_parent_id |
ELV009440992 |
| dewey-tens |
620 - Engineering 610 - Medicine & health |
| hierarchy_top_title |
Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)ELV009440992 |
| title |
Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| ctrlnum |
(DE-627)ELV034249508 (ELSEVIER)S0026-2692(14)00004-4 |
| title_full |
Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| author_sort |
Kao, Shao-Ku |
| journal |
Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
| journalStr |
Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology |
| recordtype |
marc |
| publishDateSort |
2014 |
| contenttype_str_mv |
zzz |
| container_start_page |
375 |
| author_browse |
Kao, Shao-Ku |
| container_volume |
45 |
| physical |
7 |
| class |
620 620 DE-600 610 VZ 44.85 bkl |
| format_se |
Elektronische Aufsätze |
| author-letter |
Kao, Shao-Ku |
| doi_str_mv |
10.1016/j.mejo.2014.01.003 |
| dewey-full |
620 610 |
| title_sort |
frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| title_auth |
Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| abstract |
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
| abstractGer |
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
| abstract_unstemmed |
A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V. |
| collection_details |
GBV_USEFLAG_U GBV_ELV SYSFLAG_U |
| container_issue |
4 |
| title_short |
Frequency presetting and phase error detection technique for fast-locking phase-locked loop |
| url |
https://doi.org/10.1016/j.mejo.2014.01.003 |
| remote_bool |
true |
| ppnlink |
ELV009440992 |
| mediatype_str_mv |
z |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1016/j.mejo.2014.01.003 |
| up_date |
2024-07-06T20:38:29.582Z |
| _version_ |
1803863520269303808 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV034249508</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230625200332.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">180603s2014 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.mejo.2014.01.003</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">GBVA2014022000012.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV034249508</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S0026-2692(14)00004-4</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">610</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">44.85</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kao, Shao-Ku</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Frequency presetting and phase error detection technique for fast-locking phase-locked loop</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2014transfer abstract</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">7</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Phase error detector</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Phase-locked loop</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Fast-lock</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Frequency tracking</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier Science</subfield><subfield code="a">Kokkinos, Peter ELSEVIER</subfield><subfield code="t">Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease</subfield><subfield code="d">2023</subfield><subfield code="g">Amsterdam [u.a.]</subfield><subfield code="w">(DE-627)ELV009440992</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:45</subfield><subfield code="g">year:2014</subfield><subfield code="g">number:4</subfield><subfield code="g">pages:375-381</subfield><subfield code="g">extent:7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.mejo.2014.01.003</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">44.85</subfield><subfield code="j">Kardiologie</subfield><subfield code="j">Angiologie</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">45</subfield><subfield code="j">2014</subfield><subfield code="e">4</subfield><subfield code="h">375-381</subfield><subfield code="g">7</subfield></datafield><datafield tag="953" ind1=" " ind2=" "><subfield code="2">045F</subfield><subfield code="a">620</subfield></datafield></record></collection>
|
| score |
7.400095 |