Soft error tolerant design of combinational circuits based on a local logic substitution scheme
In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probab...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Rohanipoor, Mohammad Reza [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017transfer abstract |
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| Schlagwörter: |
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| Umfang: |
12 |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
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| Übergeordnetes Werk: |
volume:67 ; year:2017 ; pages:143-154 ; extent:12 |
| Links: |
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| DOI / URN: |
10.1016/j.mejo.2017.08.006 |
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| Katalog-ID: |
ELV036220566 |
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| 245 | 1 | 0 | |a Soft error tolerant design of combinational circuits based on a local logic substitution scheme |
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| 520 | |a In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. | ||
| 520 | |a In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. | ||
| 650 | 7 | |a Soft Error Rate (SER) |2 Elsevier | |
| 650 | 7 | |a Logical masking |2 Elsevier | |
| 650 | 7 | |a Combinational circuit |2 Elsevier | |
| 650 | 7 | |a Soft error |2 Elsevier | |
| 650 | 7 | |a Partitioning |2 Elsevier | |
| 650 | 7 | |a Sub-circuit |2 Elsevier | |
| 700 | 1 | |a Ghavami, Behnam |4 oth | |
| 700 | 1 | |a Raji, Mohsen |4 oth | |
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10.1016/j.mejo.2017.08.006 doi GBVA2017022000014.pica (DE-627)ELV036220566 (ELSEVIER)S0026-2692(16)30551-1 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Rohanipoor, Mohammad Reza verfasserin aut Soft error tolerant design of combinational circuits based on a local logic substitution scheme 2017transfer abstract 12 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. Soft Error Rate (SER) Elsevier Logical masking Elsevier Combinational circuit Elsevier Soft error Elsevier Partitioning Elsevier Sub-circuit Elsevier Ghavami, Behnam oth Raji, Mohsen oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:67 year:2017 pages:143-154 extent:12 https://doi.org/10.1016/j.mejo.2017.08.006 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 67 2017 143-154 12 045F 620 |
| spelling |
10.1016/j.mejo.2017.08.006 doi GBVA2017022000014.pica (DE-627)ELV036220566 (ELSEVIER)S0026-2692(16)30551-1 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Rohanipoor, Mohammad Reza verfasserin aut Soft error tolerant design of combinational circuits based on a local logic substitution scheme 2017transfer abstract 12 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. Soft Error Rate (SER) Elsevier Logical masking Elsevier Combinational circuit Elsevier Soft error Elsevier Partitioning Elsevier Sub-circuit Elsevier Ghavami, Behnam oth Raji, Mohsen oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:67 year:2017 pages:143-154 extent:12 https://doi.org/10.1016/j.mejo.2017.08.006 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 67 2017 143-154 12 045F 620 |
| allfields_unstemmed |
10.1016/j.mejo.2017.08.006 doi GBVA2017022000014.pica (DE-627)ELV036220566 (ELSEVIER)S0026-2692(16)30551-1 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Rohanipoor, Mohammad Reza verfasserin aut Soft error tolerant design of combinational circuits based on a local logic substitution scheme 2017transfer abstract 12 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. Soft Error Rate (SER) Elsevier Logical masking Elsevier Combinational circuit Elsevier Soft error Elsevier Partitioning Elsevier Sub-circuit Elsevier Ghavami, Behnam oth Raji, Mohsen oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:67 year:2017 pages:143-154 extent:12 https://doi.org/10.1016/j.mejo.2017.08.006 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 67 2017 143-154 12 045F 620 |
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10.1016/j.mejo.2017.08.006 doi GBVA2017022000014.pica (DE-627)ELV036220566 (ELSEVIER)S0026-2692(16)30551-1 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Rohanipoor, Mohammad Reza verfasserin aut Soft error tolerant design of combinational circuits based on a local logic substitution scheme 2017transfer abstract 12 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. Soft Error Rate (SER) Elsevier Logical masking Elsevier Combinational circuit Elsevier Soft error Elsevier Partitioning Elsevier Sub-circuit Elsevier Ghavami, Behnam oth Raji, Mohsen oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:67 year:2017 pages:143-154 extent:12 https://doi.org/10.1016/j.mejo.2017.08.006 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 67 2017 143-154 12 045F 620 |
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10.1016/j.mejo.2017.08.006 doi GBVA2017022000014.pica (DE-627)ELV036220566 (ELSEVIER)S0026-2692(16)30551-1 DE-627 ger DE-627 rakwb eng 620 620 DE-600 610 VZ 44.85 bkl Rohanipoor, Mohammad Reza verfasserin aut Soft error tolerant design of combinational circuits based on a local logic substitution scheme 2017transfer abstract 12 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. Soft Error Rate (SER) Elsevier Logical masking Elsevier Combinational circuit Elsevier Soft error Elsevier Partitioning Elsevier Sub-circuit Elsevier Ghavami, Behnam oth Raji, Mohsen oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:67 year:2017 pages:143-154 extent:12 https://doi.org/10.1016/j.mejo.2017.08.006 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 67 2017 143-154 12 045F 620 |
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soft error tolerant design of combinational circuits based on a local logic substitution scheme |
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Soft error tolerant design of combinational circuits based on a local logic substitution scheme |
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In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. |
| abstractGer |
In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. |
| abstract_unstemmed |
In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6]. |
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