Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP c...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Hu, Jingtong [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2013transfer abstract |
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| Schlagwörter: |
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| Umfang: |
11 |
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| Übergeordnetes Werk: |
Enthalten in: Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile - 2012, JSA : the EUROMICRO journal, Amsterdam |
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| Übergeordnetes Werk: |
volume:59 ; year:2013 ; number:7 ; pages:389-399 ; extent:11 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.sysarc.2013.05.003 |
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| 520 | |a In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. | ||
| 520 | |a In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. | ||
| 650 | 7 | |a DSPs |2 Elsevier | |
| 650 | 7 | |a Multi-core |2 Elsevier | |
| 650 | 7 | |a Multi-level memory |2 Elsevier | |
| 650 | 7 | |a Scheduling |2 Elsevier | |
| 650 | 7 | |a Memory access |2 Elsevier | |
| 700 | 1 | |a He, Yi |4 oth | |
| 700 | 1 | |a Zhuge, Qingfeng |4 oth | |
| 700 | 1 | |a Sha, Edwin H.-M. |4 oth | |
| 700 | 1 | |a Xue, Chun Jason |4 oth | |
| 700 | 1 | |a Zhao, Yingchao |4 oth | |
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10.1016/j.sysarc.2013.05.003 doi GBVA2013002000015.pica (DE-627)ELV038524805 (ELSEVIER)S1383-7621(13)00070-2 DE-627 ger DE-627 rakwb eng 004 004 DE-600 540 VZ 610 VZ 630 VZ 22 ssgn 46.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. DSPs Elsevier Multi-core Elsevier Multi-level memory Elsevier Scheduling Elsevier Memory access Elsevier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Elsevier Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile 2012 JSA : the EUROMICRO journal Amsterdam (DE-627)ELV011208724 volume:59 year:2013 number:7 pages:389-399 extent:11 https://doi.org/10.1016/j.sysarc.2013.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U GBV_ILN_21 GBV_ILN_22 GBV_ILN_26 GBV_ILN_40 GBV_ILN_70 GBV_ILN_72 GBV_ILN_640 GBV_ILN_2001 GBV_ILN_2002 GBV_ILN_2003 GBV_ILN_2007 46.00 Tiermedizin: Allgemeines VZ AR 59 2013 7 389-399 11 045F 004 |
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10.1016/j.sysarc.2013.05.003 doi GBVA2013002000015.pica (DE-627)ELV038524805 (ELSEVIER)S1383-7621(13)00070-2 DE-627 ger DE-627 rakwb eng 004 004 DE-600 540 VZ 610 VZ 630 VZ 22 ssgn 46.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. DSPs Elsevier Multi-core Elsevier Multi-level memory Elsevier Scheduling Elsevier Memory access Elsevier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Elsevier Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile 2012 JSA : the EUROMICRO journal Amsterdam (DE-627)ELV011208724 volume:59 year:2013 number:7 pages:389-399 extent:11 https://doi.org/10.1016/j.sysarc.2013.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U GBV_ILN_21 GBV_ILN_22 GBV_ILN_26 GBV_ILN_40 GBV_ILN_70 GBV_ILN_72 GBV_ILN_640 GBV_ILN_2001 GBV_ILN_2002 GBV_ILN_2003 GBV_ILN_2007 46.00 Tiermedizin: Allgemeines VZ AR 59 2013 7 389-399 11 045F 004 |
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10.1016/j.sysarc.2013.05.003 doi GBVA2013002000015.pica (DE-627)ELV038524805 (ELSEVIER)S1383-7621(13)00070-2 DE-627 ger DE-627 rakwb eng 004 004 DE-600 540 VZ 610 VZ 630 VZ 22 ssgn 46.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. DSPs Elsevier Multi-core Elsevier Multi-level memory Elsevier Scheduling Elsevier Memory access Elsevier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Elsevier Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile 2012 JSA : the EUROMICRO journal Amsterdam (DE-627)ELV011208724 volume:59 year:2013 number:7 pages:389-399 extent:11 https://doi.org/10.1016/j.sysarc.2013.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U GBV_ILN_21 GBV_ILN_22 GBV_ILN_26 GBV_ILN_40 GBV_ILN_70 GBV_ILN_72 GBV_ILN_640 GBV_ILN_2001 GBV_ILN_2002 GBV_ILN_2003 GBV_ILN_2007 46.00 Tiermedizin: Allgemeines VZ AR 59 2013 7 389-399 11 045F 004 |
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10.1016/j.sysarc.2013.05.003 doi GBVA2013002000015.pica (DE-627)ELV038524805 (ELSEVIER)S1383-7621(13)00070-2 DE-627 ger DE-627 rakwb eng 004 004 DE-600 540 VZ 610 VZ 630 VZ 22 ssgn 46.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. DSPs Elsevier Multi-core Elsevier Multi-level memory Elsevier Scheduling Elsevier Memory access Elsevier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Elsevier Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile 2012 JSA : the EUROMICRO journal Amsterdam (DE-627)ELV011208724 volume:59 year:2013 number:7 pages:389-399 extent:11 https://doi.org/10.1016/j.sysarc.2013.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U GBV_ILN_21 GBV_ILN_22 GBV_ILN_26 GBV_ILN_40 GBV_ILN_70 GBV_ILN_72 GBV_ILN_640 GBV_ILN_2001 GBV_ILN_2002 GBV_ILN_2003 GBV_ILN_2007 46.00 Tiermedizin: Allgemeines VZ AR 59 2013 7 389-399 11 045F 004 |
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10.1016/j.sysarc.2013.05.003 doi GBVA2013002000015.pica (DE-627)ELV038524805 (ELSEVIER)S1383-7621(13)00070-2 DE-627 ger DE-627 rakwb eng 004 004 DE-600 540 VZ 610 VZ 630 VZ 22 ssgn 46.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013transfer abstract 11 nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. DSPs Elsevier Multi-core Elsevier Multi-level memory Elsevier Scheduling Elsevier Memory access Elsevier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Elsevier Discovery of a second generation agonist of the orphan G-protein coupled receptor GPR119 with an improved profile 2012 JSA : the EUROMICRO journal Amsterdam (DE-627)ELV011208724 volume:59 year:2013 number:7 pages:389-399 extent:11 https://doi.org/10.1016/j.sysarc.2013.05.003 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U GBV_ILN_21 GBV_ILN_22 GBV_ILN_26 GBV_ILN_40 GBV_ILN_70 GBV_ILN_72 GBV_ILN_640 GBV_ILN_2001 GBV_ILN_2002 GBV_ILN_2003 GBV_ILN_2007 46.00 Tiermedizin: Allgemeines VZ AR 59 2013 7 389-399 11 045F 004 |
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In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. |
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In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. |
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In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened. |
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