A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics
In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming ye...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Honaryar, Masoud [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2021transfer abstract |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Editorial Board - 2016, München |
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| Übergeordnetes Werk: |
volume:137 ; year:2021 ; pages:0 |
| Links: |
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| DOI / URN: |
10.1016/j.aeue.2021.153804 |
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ELV054353556 |
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| 520 | |a In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. | ||
| 520 | |a In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. | ||
| 650 | 7 | |a Binary Schmitt Trigger |2 Elsevier | |
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| 650 | 7 | |a Ternary Schmitt Trigger |2 Elsevier | |
| 650 | 7 | |a CNFET |2 Elsevier | |
| 650 | 7 | |a Lower Trigger Point |2 Elsevier | |
| 700 | 1 | |a Hosseini, Seied Ali |4 oth | |
| 700 | 1 | |a Pishgar Komleh, Seyyed Hossein |4 oth | |
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10.1016/j.aeue.2021.153804 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001442.pica (DE-627)ELV054353556 (ELSEVIER)S1434-8411(21)00201-6 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Honaryar, Masoud verfasserin aut A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. Binary Schmitt Trigger Elsevier Upper Trigger Point Elsevier Carbon Nanotube Elsevier Ternary Schmitt Trigger Elsevier CNFET Elsevier Lower Trigger Point Elsevier Hosseini, Seied Ali oth Pishgar Komleh, Seyyed Hossein oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:137 year:2021 pages:0 https://doi.org/10.1016/j.aeue.2021.153804 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 137 2021 0 |
| spelling |
10.1016/j.aeue.2021.153804 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001442.pica (DE-627)ELV054353556 (ELSEVIER)S1434-8411(21)00201-6 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Honaryar, Masoud verfasserin aut A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. Binary Schmitt Trigger Elsevier Upper Trigger Point Elsevier Carbon Nanotube Elsevier Ternary Schmitt Trigger Elsevier CNFET Elsevier Lower Trigger Point Elsevier Hosseini, Seied Ali oth Pishgar Komleh, Seyyed Hossein oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:137 year:2021 pages:0 https://doi.org/10.1016/j.aeue.2021.153804 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 137 2021 0 |
| allfields_unstemmed |
10.1016/j.aeue.2021.153804 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001442.pica (DE-627)ELV054353556 (ELSEVIER)S1434-8411(21)00201-6 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Honaryar, Masoud verfasserin aut A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. Binary Schmitt Trigger Elsevier Upper Trigger Point Elsevier Carbon Nanotube Elsevier Ternary Schmitt Trigger Elsevier CNFET Elsevier Lower Trigger Point Elsevier Hosseini, Seied Ali oth Pishgar Komleh, Seyyed Hossein oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:137 year:2021 pages:0 https://doi.org/10.1016/j.aeue.2021.153804 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 137 2021 0 |
| allfieldsGer |
10.1016/j.aeue.2021.153804 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001442.pica (DE-627)ELV054353556 (ELSEVIER)S1434-8411(21)00201-6 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Honaryar, Masoud verfasserin aut A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. Binary Schmitt Trigger Elsevier Upper Trigger Point Elsevier Carbon Nanotube Elsevier Ternary Schmitt Trigger Elsevier CNFET Elsevier Lower Trigger Point Elsevier Hosseini, Seied Ali oth Pishgar Komleh, Seyyed Hossein oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:137 year:2021 pages:0 https://doi.org/10.1016/j.aeue.2021.153804 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 137 2021 0 |
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10.1016/j.aeue.2021.153804 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001442.pica (DE-627)ELV054353556 (ELSEVIER)S1434-8411(21)00201-6 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Honaryar, Masoud verfasserin aut A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. Binary Schmitt Trigger Elsevier Upper Trigger Point Elsevier Carbon Nanotube Elsevier Ternary Schmitt Trigger Elsevier CNFET Elsevier Lower Trigger Point Elsevier Hosseini, Seied Ali oth Pishgar Komleh, Seyyed Hossein oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:137 year:2021 pages:0 https://doi.org/10.1016/j.aeue.2021.153804 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 137 2021 0 |
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A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics |
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In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. |
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In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. |
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In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations. |
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