A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer
A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 2...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Tang, Xiaoke [verfasserIn] |
|---|
| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2021transfer abstract |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease - Kokkinos, Peter ELSEVIER, 2023, Amsterdam [u.a.] |
|---|---|
| Übergeordnetes Werk: |
volume:116 ; year:2021 ; pages:0 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.mejo.2021.105158 |
|---|
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| 245 | 1 | 0 | |a A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer |
| 264 | 1 | |c 2021transfer abstract | |
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| 520 | |a A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. | ||
| 520 | |a A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. | ||
| 650 | 7 | |a Phase lock loops (PLL) |2 Elsevier | |
| 650 | 7 | |a Frequency synthesizer (FS) |2 Elsevier | |
| 650 | 7 | |a Injection locked |2 Elsevier | |
| 650 | 7 | |a Phase interpolator |2 Elsevier | |
| 700 | 1 | |a Zhao, Xu |4 oth | |
| 700 | 1 | |a Hu, Ang |4 oth | |
| 700 | 1 | |a Liu, Dongsheng |4 oth | |
| 700 | 1 | |a Jin, Zirui |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier Science |a Kokkinos, Peter ELSEVIER |t Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |d 2023 |g Amsterdam [u.a.] |w (DE-627)ELV009440992 |
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10.1016/j.mejo.2021.105158 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001614.pica (DE-627)ELV055243916 (ELSEVIER)S0026-2692(21)00169-5 DE-627 ger DE-627 rakwb eng 610 VZ 44.85 bkl Tang, Xiaoke verfasserin aut A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. Phase lock loops (PLL) Elsevier Frequency synthesizer (FS) Elsevier Injection locked Elsevier Phase interpolator Elsevier Zhao, Xu oth Hu, Ang oth Liu, Dongsheng oth Jin, Zirui oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:116 year:2021 pages:0 https://doi.org/10.1016/j.mejo.2021.105158 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 116 2021 0 |
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10.1016/j.mejo.2021.105158 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001614.pica (DE-627)ELV055243916 (ELSEVIER)S0026-2692(21)00169-5 DE-627 ger DE-627 rakwb eng 610 VZ 44.85 bkl Tang, Xiaoke verfasserin aut A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. Phase lock loops (PLL) Elsevier Frequency synthesizer (FS) Elsevier Injection locked Elsevier Phase interpolator Elsevier Zhao, Xu oth Hu, Ang oth Liu, Dongsheng oth Jin, Zirui oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:116 year:2021 pages:0 https://doi.org/10.1016/j.mejo.2021.105158 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 116 2021 0 |
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10.1016/j.mejo.2021.105158 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001614.pica (DE-627)ELV055243916 (ELSEVIER)S0026-2692(21)00169-5 DE-627 ger DE-627 rakwb eng 610 VZ 44.85 bkl Tang, Xiaoke verfasserin aut A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. Phase lock loops (PLL) Elsevier Frequency synthesizer (FS) Elsevier Injection locked Elsevier Phase interpolator Elsevier Zhao, Xu oth Hu, Ang oth Liu, Dongsheng oth Jin, Zirui oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:116 year:2021 pages:0 https://doi.org/10.1016/j.mejo.2021.105158 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 116 2021 0 |
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10.1016/j.mejo.2021.105158 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001614.pica (DE-627)ELV055243916 (ELSEVIER)S0026-2692(21)00169-5 DE-627 ger DE-627 rakwb eng 610 VZ 44.85 bkl Tang, Xiaoke verfasserin aut A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. Phase lock loops (PLL) Elsevier Frequency synthesizer (FS) Elsevier Injection locked Elsevier Phase interpolator Elsevier Zhao, Xu oth Hu, Ang oth Liu, Dongsheng oth Jin, Zirui oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:116 year:2021 pages:0 https://doi.org/10.1016/j.mejo.2021.105158 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 116 2021 0 |
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10.1016/j.mejo.2021.105158 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001614.pica (DE-627)ELV055243916 (ELSEVIER)S0026-2692(21)00169-5 DE-627 ger DE-627 rakwb eng 610 VZ 44.85 bkl Tang, Xiaoke verfasserin aut A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer 2021transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. Phase lock loops (PLL) Elsevier Frequency synthesizer (FS) Elsevier Injection locked Elsevier Phase interpolator Elsevier Zhao, Xu oth Hu, Ang oth Liu, Dongsheng oth Jin, Zirui oth Enthalten in Elsevier Science Kokkinos, Peter ELSEVIER Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease 2023 Amsterdam [u.a.] (DE-627)ELV009440992 volume:116 year:2021 pages:0 https://doi.org/10.1016/j.mejo.2021.105158 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U 44.85 Kardiologie Angiologie VZ AR 116 2021 0 |
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The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. 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Changes in Cardiorespiratory Fitness and Survival in Patients With or Without Cardiovascular Disease |
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a 433/2400 mhz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer |
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A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer |
| abstract |
A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. |
| abstractGer |
A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. |
| abstract_unstemmed |
A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW. |
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A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer |
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