A 13.8pJ/conv-step binary search ADC with reusable comparator architecture
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8...
Ausführliche Beschreibung
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Dipti [verfasserIn] |
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Englisch |
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2022transfer abstract |
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Enthalten in: Editorial Board - 2016, München |
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volume:144 ; year:2022 ; pages:0 |
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DOI / URN: |
10.1016/j.aeue.2021.154056 |
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ELV056308108 |
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520 | |a This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. | ||
520 | |a This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. | ||
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10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
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10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
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10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
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10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
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10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
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A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
abstract |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
abstractGer |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
abstract_unstemmed |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
collection_details |
GBV_USEFLAG_U GBV_ELV SYSFLAG_U |
title_short |
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
url |
https://doi.org/10.1016/j.aeue.2021.154056 |
remote_bool |
true |
author2 |
Singh, Sajai Vir Kumawat, Tushar Bekal, Anush Misra, Prasanna Kumar Goswami, Manish |
author2Str |
Singh, Sajai Vir Kumawat, Tushar Bekal, Anush Misra, Prasanna Kumar Goswami, Manish |
ppnlink |
ELV019902425 |
mediatype_str_mv |
z |
isOA_txt |
false |
hochschulschrift_bool |
false |
author2_role |
oth oth oth oth oth |
doi_str |
10.1016/j.aeue.2021.154056 |
up_date |
2024-07-06T20:00:51.329Z |
_version_ |
1803861152320454656 |
fullrecord_marcxml |
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|
score |
7.400629 |