A 13.8pJ/conv-step binary search ADC with reusable comparator architecture
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Dipti [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2022transfer abstract |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Editorial Board - 2016, München |
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| Übergeordnetes Werk: |
volume:144 ; year:2022 ; pages:0 |
| Links: |
|---|
| DOI / URN: |
10.1016/j.aeue.2021.154056 |
|---|
| Katalog-ID: |
ELV056308108 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | ELV056308108 | ||
| 003 | DE-627 | ||
| 005 | 20230626043055.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 220105s2022 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1016/j.aeue.2021.154056 |2 doi | |
| 028 | 5 | 2 | |a /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica |
| 035 | |a (DE-627)ELV056308108 | ||
| 035 | |a (ELSEVIER)S1434-8411(21)00453-2 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 610 |q VZ |
| 082 | 0 | 4 | |a 370 |q VZ |
| 100 | 1 | |a Dipti |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| 264 | 1 | |c 2022transfer abstract | |
| 336 | |a nicht spezifiziert |b zzz |2 rdacontent | ||
| 337 | |a nicht spezifiziert |b z |2 rdamedia | ||
| 338 | |a nicht spezifiziert |b zu |2 rdacarrier | ||
| 520 | |a This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. | ||
| 520 | |a This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. | ||
| 650 | 7 | |a Asynchronous |2 Elsevier | |
| 650 | 7 | |a Signal to noise ratio (SNR) |2 Elsevier | |
| 650 | 7 | |a Analog to digital converter (ADC) |2 Elsevier | |
| 650 | 7 | |a Binary search (BS) ADC |2 Elsevier | |
| 700 | 1 | |a Singh, Sajai Vir |4 oth | |
| 700 | 1 | |a Kumawat, Tushar |4 oth | |
| 700 | 1 | |a Bekal, Anush |4 oth | |
| 700 | 1 | |a Misra, Prasanna Kumar |4 oth | |
| 700 | 1 | |a Goswami, Manish |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |n Elsevier |t Editorial Board |d 2016 |g München |w (DE-627)ELV019902425 |
| 773 | 1 | 8 | |g volume:144 |g year:2022 |g pages:0 |
| 856 | 4 | 0 | |u https://doi.org/10.1016/j.aeue.2021.154056 |3 Volltext |
| 912 | |a GBV_USEFLAG_U | ||
| 912 | |a GBV_ELV | ||
| 912 | |a SYSFLAG_U | ||
| 951 | |a AR | ||
| 952 | |d 144 |j 2022 |h 0 | ||
| author_variant |
d |
|---|---|
| matchkey_str |
diptisinghsajaivirkumawattusharbekalanus:2022----:18jovtpiayerhdwtrualcm |
| hierarchy_sort_str |
2022transfer abstract |
| publishDate |
2022 |
| allfields |
10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
| spelling |
10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
| allfields_unstemmed |
10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
| allfieldsGer |
10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
| allfieldsSound |
10.1016/j.aeue.2021.154056 doi /cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica (DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 DE-627 ger DE-627 rakwb eng 610 VZ 370 VZ Dipti verfasserin aut A 13.8pJ/conv-step binary search ADC with reusable comparator architecture 2022transfer abstract nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier Singh, Sajai Vir oth Kumawat, Tushar oth Bekal, Anush oth Misra, Prasanna Kumar oth Goswami, Manish oth Enthalten in Elsevier Editorial Board 2016 München (DE-627)ELV019902425 volume:144 year:2022 pages:0 https://doi.org/10.1016/j.aeue.2021.154056 Volltext GBV_USEFLAG_U GBV_ELV SYSFLAG_U AR 144 2022 0 |
| language |
English |
| source |
Enthalten in Editorial Board München volume:144 year:2022 pages:0 |
| sourceStr |
Enthalten in Editorial Board München volume:144 year:2022 pages:0 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Asynchronous Signal to noise ratio (SNR) Analog to digital converter (ADC) Binary search (BS) ADC |
| dewey-raw |
610 |
| isfreeaccess_bool |
false |
| container_title |
Editorial Board |
| authorswithroles_txt_mv |
Dipti @@aut@@ Singh, Sajai Vir @@oth@@ Kumawat, Tushar @@oth@@ Bekal, Anush @@oth@@ Misra, Prasanna Kumar @@oth@@ Goswami, Manish @@oth@@ |
| publishDateDaySort_date |
2022-01-01T00:00:00Z |
| hierarchy_top_id |
ELV019902425 |
| dewey-sort |
3610 |
| id |
ELV056308108 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV056308108</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230626043055.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220105s2022 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.aeue.2021.154056</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">/cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV056308108</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S1434-8411(21)00453-2</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">610</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">370</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dipti</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A 13.8pJ/conv-step binary search ADC with reusable comparator architecture</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2022transfer abstract</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Asynchronous</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Signal to noise ratio (SNR)</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Analog to digital converter (ADC)</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Binary search (BS) ADC</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Singh, Sajai Vir</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kumawat, Tushar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bekal, Anush</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Misra, Prasanna Kumar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Goswami, Manish</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier</subfield><subfield code="t">Editorial Board</subfield><subfield code="d">2016</subfield><subfield code="g">München</subfield><subfield code="w">(DE-627)ELV019902425</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:144</subfield><subfield code="g">year:2022</subfield><subfield code="g">pages:0</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.aeue.2021.154056</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">144</subfield><subfield code="j">2022</subfield><subfield code="h">0</subfield></datafield></record></collection>
|
| author |
Dipti |
| spellingShingle |
Dipti ddc 610 ddc 370 Elsevier Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| authorStr |
Dipti |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)ELV019902425 |
| format |
electronic Article |
| dewey-ones |
610 - Medicine & health 370 - Education |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
elsevier |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
610 VZ 370 VZ A 13.8pJ/conv-step binary search ADC with reusable comparator architecture Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC Elsevier |
| topic |
ddc 610 ddc 370 Elsevier Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC |
| topic_unstemmed |
ddc 610 ddc 370 Elsevier Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC |
| topic_browse |
ddc 610 ddc 370 Elsevier Asynchronous Elsevier Signal to noise ratio (SNR) Elsevier Analog to digital converter (ADC) Elsevier Binary search (BS) ADC |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
zu |
| author2_variant |
s v s sv svs t k tk a b ab p k m pk pkm m g mg |
| hierarchy_parent_title |
Editorial Board |
| hierarchy_parent_id |
ELV019902425 |
| dewey-tens |
610 - Medicine & health 370 - Education |
| hierarchy_top_title |
Editorial Board |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)ELV019902425 |
| title |
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| ctrlnum |
(DE-627)ELV056308108 (ELSEVIER)S1434-8411(21)00453-2 |
| title_full |
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| author_sort |
Dipti |
| journal |
Editorial Board |
| journalStr |
Editorial Board |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology 300 - Social sciences |
| recordtype |
marc |
| publishDateSort |
2022 |
| contenttype_str_mv |
zzz |
| container_start_page |
0 |
| author_browse |
Dipti |
| container_volume |
144 |
| class |
610 VZ 370 VZ |
| format_se |
Elektronische Aufsätze |
| author-letter |
Dipti |
| doi_str_mv |
10.1016/j.aeue.2021.154056 |
| dewey-full |
610 370 |
| title_sort |
a 13.8pj/conv-step binary search adc with reusable comparator architecture |
| title_auth |
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| abstract |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
| abstractGer |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
| abstract_unstemmed |
This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. |
| collection_details |
GBV_USEFLAG_U GBV_ELV SYSFLAG_U |
| title_short |
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture |
| url |
https://doi.org/10.1016/j.aeue.2021.154056 |
| remote_bool |
true |
| author2 |
Singh, Sajai Vir Kumawat, Tushar Bekal, Anush Misra, Prasanna Kumar Goswami, Manish |
| author2Str |
Singh, Sajai Vir Kumawat, Tushar Bekal, Anush Misra, Prasanna Kumar Goswami, Manish |
| ppnlink |
ELV019902425 |
| mediatype_str_mv |
z |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth oth oth oth |
| doi_str |
10.1016/j.aeue.2021.154056 |
| up_date |
2024-07-06T20:00:51.329Z |
| _version_ |
1803861152320454656 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">ELV056308108</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230626043055.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220105s2022 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1016/j.aeue.2021.154056</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">/cbs_pica/cbs_olc/import_discovery/elsevier/einzuspielen/GBV00000000001623.pica</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)ELV056308108</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ELSEVIER)S1434-8411(21)00453-2</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">610</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">370</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dipti</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A 13.8pJ/conv-step binary search ADC with reusable comparator architecture</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2022transfer abstract</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Asynchronous</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Signal to noise ratio (SNR)</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Analog to digital converter (ADC)</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Binary search (BS) ADC</subfield><subfield code="2">Elsevier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Singh, Sajai Vir</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kumawat, Tushar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bekal, Anush</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Misra, Prasanna Kumar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Goswami, Manish</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="n">Elsevier</subfield><subfield code="t">Editorial Board</subfield><subfield code="d">2016</subfield><subfield code="g">München</subfield><subfield code="w">(DE-627)ELV019902425</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:144</subfield><subfield code="g">year:2022</subfield><subfield code="g">pages:0</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1016/j.aeue.2021.154056</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_U</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ELV</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_U</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">144</subfield><subfield code="j">2022</subfield><subfield code="h">0</subfield></datafield></record></collection>
|
| score |
7.400629 |