The Synthesis of Stochastic Circuits for Nanoscale Computation
Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Al...
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| Autor*in: |
Qian, Weikang [verfasserIn] Backes, John [author] Riedel, Marc D. [author] |
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| Format: |
E-Artikel |
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Englisch |
| Erschienen: |
2009 |
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Online-Ressource |
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IGI Global InfoSci Journals Archive 2000 - 2012 |
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| Übergeordnetes Werk: |
In: International journal of nanotechnology and molecular computation - Hershey, Pa : IGI Global, 2009, 1(2009), 4, Seite 39-57 |
| Übergeordnetes Werk: |
volume:1 ; year:2009 ; number:4 ; pages:39-57 |
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| DOI / URN: |
10.4018/jnmc.2009120903 |
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10.4018/jnmc.2009120903 doi (DE-627)NLEJ24449486X (VZGNL)10.4018/jnmc.2009120903 DE-627 ger DE-627 rakwb eng Qian, Weikang verfasserin aut The Synthesis of Stochastic Circuits for Nanoscale Computation 2009 Online-Ressource nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively IGI Global InfoSci Journals Archive 2000 - 2012 Nanoscale Computation Nanowires Nanowire Arrays Stochastic Circuits Backes, John author aut Riedel, Marc D. author aut In International journal of nanotechnology and molecular computation Hershey, Pa : IGI Global, 2009 1(2009), 4, Seite 39-57 Online-Ressource (DE-627)NLEJ244419361 (DE-600)2703570-0 1941-6326 nnns volume:1 year:2009 number:4 pages:39-57 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903&buylink=true text/html Abstract Deutschlandweit zugänglich ZDB-1-GIS GBV_NL_ARTICLE AR 1 2009 4 39-57 |
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10.4018/jnmc.2009120903 doi (DE-627)NLEJ24449486X (VZGNL)10.4018/jnmc.2009120903 DE-627 ger DE-627 rakwb eng Qian, Weikang verfasserin aut The Synthesis of Stochastic Circuits for Nanoscale Computation 2009 Online-Ressource nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively IGI Global InfoSci Journals Archive 2000 - 2012 Nanoscale Computation Nanowires Nanowire Arrays Stochastic Circuits Backes, John author aut Riedel, Marc D. author aut In International journal of nanotechnology and molecular computation Hershey, Pa : IGI Global, 2009 1(2009), 4, Seite 39-57 Online-Ressource (DE-627)NLEJ244419361 (DE-600)2703570-0 1941-6326 nnns volume:1 year:2009 number:4 pages:39-57 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903&buylink=true text/html Abstract Deutschlandweit zugänglich ZDB-1-GIS GBV_NL_ARTICLE AR 1 2009 4 39-57 |
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10.4018/jnmc.2009120903 doi (DE-627)NLEJ24449486X (VZGNL)10.4018/jnmc.2009120903 DE-627 ger DE-627 rakwb eng Qian, Weikang verfasserin aut The Synthesis of Stochastic Circuits for Nanoscale Computation 2009 Online-Ressource nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively IGI Global InfoSci Journals Archive 2000 - 2012 Nanoscale Computation Nanowires Nanowire Arrays Stochastic Circuits Backes, John author aut Riedel, Marc D. author aut In International journal of nanotechnology and molecular computation Hershey, Pa : IGI Global, 2009 1(2009), 4, Seite 39-57 Online-Ressource (DE-627)NLEJ244419361 (DE-600)2703570-0 1941-6326 nnns volume:1 year:2009 number:4 pages:39-57 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903&buylink=true text/html Abstract Deutschlandweit zugänglich ZDB-1-GIS GBV_NL_ARTICLE AR 1 2009 4 39-57 |
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10.4018/jnmc.2009120903 doi (DE-627)NLEJ24449486X (VZGNL)10.4018/jnmc.2009120903 DE-627 ger DE-627 rakwb eng Qian, Weikang verfasserin aut The Synthesis of Stochastic Circuits for Nanoscale Computation 2009 Online-Ressource nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively IGI Global InfoSci Journals Archive 2000 - 2012 Nanoscale Computation Nanowires Nanowire Arrays Stochastic Circuits Backes, John author aut Riedel, Marc D. author aut In International journal of nanotechnology and molecular computation Hershey, Pa : IGI Global, 2009 1(2009), 4, Seite 39-57 Online-Ressource (DE-627)NLEJ244419361 (DE-600)2703570-0 1941-6326 nnns volume:1 year:2009 number:4 pages:39-57 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903&buylink=true text/html Abstract Deutschlandweit zugänglich ZDB-1-GIS GBV_NL_ARTICLE AR 1 2009 4 39-57 |
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10.4018/jnmc.2009120903 doi (DE-627)NLEJ24449486X (VZGNL)10.4018/jnmc.2009120903 DE-627 ger DE-627 rakwb eng Qian, Weikang verfasserin aut The Synthesis of Stochastic Circuits for Nanoscale Computation 2009 Online-Ressource nicht spezifiziert zzz rdacontent nicht spezifiziert z rdamedia nicht spezifiziert zu rdacarrier Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively IGI Global InfoSci Journals Archive 2000 - 2012 Nanoscale Computation Nanowires Nanowire Arrays Stochastic Circuits Backes, John author aut Riedel, Marc D. author aut In International journal of nanotechnology and molecular computation Hershey, Pa : IGI Global, 2009 1(2009), 4, Seite 39-57 Online-Ressource (DE-627)NLEJ244419361 (DE-600)2703570-0 1941-6326 nnns volume:1 year:2009 number:4 pages:39-57 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jnmc.2009120903&buylink=true text/html Abstract Deutschlandweit zugänglich ZDB-1-GIS GBV_NL_ARTICLE AR 1 2009 4 39-57 |
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Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively |
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Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively |
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Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">NLEJ24449486X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20240202180225.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">150605s2009 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.4018/jnmc.2009120903</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)NLEJ24449486X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(VZGNL)10.4018/jnmc.2009120903</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Qian, Weikang</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="4"><subfield code="a">The Synthesis of Stochastic Circuits for Nanoscale Computation</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zzz</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">z</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">nicht spezifiziert</subfield><subfield code="b">zu</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. 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