A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC
This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Further...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Tatas, K. [verfasserIn] Siozios, K. [verfasserIn] Bartzas, A. [verfasserIn] Kyriacou, C. [verfasserIn] Soudris, D. [verfasserIn] |
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| Sprache: |
Englisch |
| Erschienen: |
2013 |
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| Umfang: |
1 Online-Ressource |
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Enthalten in: International journal of adaptive, resilient and autonomic systems - Hershey, Pa : IGI Global, 2010, 4(2013), 3, Seite 1-24 |
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| Übergeordnetes Werk: |
volume:4 ; year:2013 ; number:3 ; pages:1-24 |
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| DOI / URN: |
10.4018/jaras.2013070101 |
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NLEJ251787710 |
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10.4018/jaras.2013070101 doi (DE-627)NLEJ251787710 (VZGNL)10.4018/jaras.2013070101 DE-627 ger DE-627 rakwb eng Tatas, K. verfasserin aut A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach Field-Programmable Gate Array (FPGA) High-Level Exploration Network-on-Chip (NoC) NoC Prototyping Three-Dimensional (3D) Chips Siozios, K. verfasserin aut Bartzas, A. verfasserin aut Kyriacou, C. verfasserin aut Soudris, D. verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 1-24 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:1-24 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 1-24 |
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10.4018/jaras.2013070101 doi (DE-627)NLEJ251787710 (VZGNL)10.4018/jaras.2013070101 DE-627 ger DE-627 rakwb eng Tatas, K. verfasserin aut A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach Field-Programmable Gate Array (FPGA) High-Level Exploration Network-on-Chip (NoC) NoC Prototyping Three-Dimensional (3D) Chips Siozios, K. verfasserin aut Bartzas, A. verfasserin aut Kyriacou, C. verfasserin aut Soudris, D. verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 1-24 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:1-24 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 1-24 |
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10.4018/jaras.2013070101 doi (DE-627)NLEJ251787710 (VZGNL)10.4018/jaras.2013070101 DE-627 ger DE-627 rakwb eng Tatas, K. verfasserin aut A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach Field-Programmable Gate Array (FPGA) High-Level Exploration Network-on-Chip (NoC) NoC Prototyping Three-Dimensional (3D) Chips Siozios, K. verfasserin aut Bartzas, A. verfasserin aut Kyriacou, C. verfasserin aut Soudris, D. verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 1-24 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:1-24 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 1-24 |
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10.4018/jaras.2013070101 doi (DE-627)NLEJ251787710 (VZGNL)10.4018/jaras.2013070101 DE-627 ger DE-627 rakwb eng Tatas, K. verfasserin aut A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach Field-Programmable Gate Array (FPGA) High-Level Exploration Network-on-Chip (NoC) NoC Prototyping Three-Dimensional (3D) Chips Siozios, K. verfasserin aut Bartzas, A. verfasserin aut Kyriacou, C. verfasserin aut Soudris, D. verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 1-24 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:1-24 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 1-24 |
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10.4018/jaras.2013070101 doi (DE-627)NLEJ251787710 (VZGNL)10.4018/jaras.2013070101 DE-627 ger DE-627 rakwb eng Tatas, K. verfasserin aut A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach Field-Programmable Gate Array (FPGA) High-Level Exploration Network-on-Chip (NoC) NoC Prototyping Three-Dimensional (3D) Chips Siozios, K. verfasserin aut Bartzas, A. verfasserin aut Kyriacou, C. verfasserin aut Soudris, D. verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 1-24 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:1-24 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 1-24 |
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This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach |
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This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach |
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This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">NLEJ251787710</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20231205143831.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">231128s2013 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.4018/jaras.2013070101</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)NLEJ251787710</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(VZGNL)10.4018/jaras.2013070101</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Tatas, K.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2013</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Field-Programmable Gate Array (FPGA)</subfield><subfield code="a">High-Level Exploration</subfield><subfield code="a">Network-on-Chip (NoC)</subfield><subfield code="a">NoC Prototyping</subfield><subfield code="a">Three-Dimensional (3D) Chips</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Siozios, K.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bartzas, A.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kyriacou, C.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Soudris, D.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">International journal of adaptive, resilient and autonomic systems</subfield><subfield code="d">Hershey, Pa : IGI Global, 2010</subfield><subfield code="g">4(2013), 3, Seite 1-24</subfield><subfield code="h">Online-Ressource</subfield><subfield code="w">(DE-627)NLEJ244418640</subfield><subfield code="w">(DE-600)2695784-X</subfield><subfield code="x">1947-9239</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:4</subfield><subfield code="g">year:2013</subfield><subfield code="g">number:3</subfield><subfield code="g">pages:1-24</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101</subfield><subfield code="m">X:IGIG</subfield><subfield code="x">Verlag</subfield><subfield code="z">Deutschlandweit zugänglich</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070101&buylink=true</subfield><subfield code="3">Abstract</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-1-GIS</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_NL_ARTICLE</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">4</subfield><subfield code="j">2013</subfield><subfield code="e">3</subfield><subfield code="h">1-24</subfield></datafield></record></collection>
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