Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems
Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperat...
Ausführliche Beschreibung
Autor*in: |
Vaddina, Kameswar Rao [verfasserIn] Liljeberg, Pasi [verfasserIn] Plosila, Juha [verfasserIn] |
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E-Artikel |
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Sprache: |
Englisch |
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2013 |
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Umfang: |
1 Online-Ressource |
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Übergeordnetes Werk: |
Enthalten in: International journal of adaptive, resilient and autonomic systems - Hershey, Pa : IGI Global, 2010, 4(2013), 3, Seite 61-81 |
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Übergeordnetes Werk: |
volume:4 ; year:2013 ; number:3 ; pages:61-81 |
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DOI / URN: |
10.4018/jaras.2013070104 |
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10.4018/jaras.2013070104 doi (DE-627)NLEJ251787745 (VZGNL)10.4018/jaras.2013070104 DE-627 ger DE-627 rakwb eng Vaddina, Kameswar Rao verfasserin aut Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping Hotspots Stacked Integrated Circuits (ICs) Thermal Analysis Thermal Management Thermal Modeling Three-Dimensional (3D) Networks-on-Chip Liljeberg, Pasi verfasserin aut Plosila, Juha verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 61-81 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:61-81 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 61-81 |
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10.4018/jaras.2013070104 doi (DE-627)NLEJ251787745 (VZGNL)10.4018/jaras.2013070104 DE-627 ger DE-627 rakwb eng Vaddina, Kameswar Rao verfasserin aut Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping Hotspots Stacked Integrated Circuits (ICs) Thermal Analysis Thermal Management Thermal Modeling Three-Dimensional (3D) Networks-on-Chip Liljeberg, Pasi verfasserin aut Plosila, Juha verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 61-81 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:61-81 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 61-81 |
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10.4018/jaras.2013070104 doi (DE-627)NLEJ251787745 (VZGNL)10.4018/jaras.2013070104 DE-627 ger DE-627 rakwb eng Vaddina, Kameswar Rao verfasserin aut Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping Hotspots Stacked Integrated Circuits (ICs) Thermal Analysis Thermal Management Thermal Modeling Three-Dimensional (3D) Networks-on-Chip Liljeberg, Pasi verfasserin aut Plosila, Juha verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 61-81 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:61-81 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 61-81 |
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10.4018/jaras.2013070104 doi (DE-627)NLEJ251787745 (VZGNL)10.4018/jaras.2013070104 DE-627 ger DE-627 rakwb eng Vaddina, Kameswar Rao verfasserin aut Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems 2013 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping Hotspots Stacked Integrated Circuits (ICs) Thermal Analysis Thermal Management Thermal Modeling Three-Dimensional (3D) Networks-on-Chip Liljeberg, Pasi verfasserin aut Plosila, Juha verfasserin aut Enthalten in International journal of adaptive, resilient and autonomic systems Hershey, Pa : IGI Global, 2010 4(2013), 3, Seite 61-81 Online-Ressource (DE-627)NLEJ244418640 (DE-600)2695784-X 1947-9239 nnns volume:4 year:2013 number:3 pages:61-81 http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104 X:IGIG Verlag Deutschlandweit zugänglich http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jaras.2013070104&buylink=true Abstract ZDB-1-GIS GBV_NL_ARTICLE AR 4 2013 3 61-81 |
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Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping |
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Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping |
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Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping |
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Liljeberg, Pasi Plosila, Juha |
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doi_str |
10.4018/jaras.2013070104 |
up_date |
2024-07-06T11:36:31.765Z |
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