Reconfigurable Architectures Workshop (RAW 2000) - Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints

Gespeichert in:

Autor*in:	Lakshmikanthan, P. [verfasserIn] Govindarajan, S. Srinivasan, V. Vemuri, R.

Format:	Artikel

Erschienen:	2000

Umfang:	8

Übergeordnetes Werk:	Enthalten in: Lecture notes in computer science - Berlin, Germany : Springer, 1973, 1800(2000), Seite 924-931
Übergeordnetes Werk:	volume:1800 ; year:2000 ; pages:924-931 ; extent:8

Katalog-ID:	OLC1573111503

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