A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip

Gespeichert in:

Autor*in:	Santos, D.M. [verfasserIn] Dow, S.F. Levi, M.E.

Format:	Artikel

Erschienen:	1996

Umfang:	3

Übergeordnetes Werk:	Enthalten in: IEEE transactions on nuclear science - New York, NY : IEEE, 1963, 43(1996), 3, 2, Seite 1717-1719
Übergeordnetes Werk:	volume:43 ; year:1996 ; number:3 ; supplement:2 ; pages:1717-1719 ; extent:3

Katalog-ID:	OLC1598186531

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A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip

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