PAPERS - Timing - Timed Circuit Verification Using TEL Structures

Gespeichert in:

Autor*in:	Belluomini, W. [verfasserIn] Myers, C.J. Hofstee, H.P.

Format:	Artikel

Erschienen:	2001

Umfang:	18

Übergeordnetes Werk:	Enthalten in: IEEE transactions on computer-aided design of integrated circuits and systems - New York, NY : Institute of Electrical and Electronics Engineers, 1982, 20(2001), 1, Seite 129-146
Übergeordnetes Werk:	volume:20 ; year:2001 ; number:1 ; pages:129-146 ; extent:18

Katalog-ID:	OLC1600509983

Internformat


LEADER	01000caa a22002652 4500
001	OLC1600509983
003	DE-627
005	20210701123533.0
007	tu
008	010313s2001 xx \|\|\|\|\| 00\| \|\|und c
028	5	2	\|a SW010313
035			\|a (DE-627)OLC1600509983
035			\|a (DE-599)GBVOLC1600509983
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
082	0	4	\|a 620
100	1		\|a Belluomini, W. \|e verfasserin \|4 aut
245	1	0	\|a PAPERS - Timing - Timed Circuit Verification Using TEL Structures
264		1	\|c 2001
300			\|a 18
336			\|a Text \|b txt \|2 rdacontent
337			\|a ohne Hilfsmittel zu benutzen \|b n \|2 rdamedia
338			\|a Band \|b nc \|2 rdacarrier
700	1		\|a Myers, C.J. \|4 oth
700	1		\|a Hofstee, H.P. \|4 oth
773	0	8	\|i Enthalten in \|t IEEE transactions on computer-aided design of integrated circuits and systems \|d New York, NY : Institute of Electrical and Electronics Engineers, 1982 \|g 20(2001), 1, Seite 129-146 \|w (DE-627)13041705X \|w (DE-600)627344-0 \|w (DE-576)015919471 \|x 0278-0070 \|7 nnns
773	1	8	\|g volume:20 \|g year:2001 \|g number:1 \|g pages:129-146 \|g extent:18
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_OLC
912			\|a SSG-OLC-TEC
912			\|a SSG-OLC-PHY
912			\|a SSG-OLC-MAT
912			\|a GBV_ILN_11
912			\|a GBV_ILN_20
912			\|a GBV_ILN_21
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_32
912			\|a GBV_ILN_62
912			\|a GBV_ILN_65
912			\|a GBV_ILN_70
912			\|a GBV_ILN_100
912			\|a GBV_ILN_120
912			\|a GBV_ILN_285
912			\|a GBV_ILN_2002
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2006
912			\|a GBV_ILN_2010
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2015
912			\|a GBV_ILN_2020
912			\|a GBV_ILN_2021
912			\|a GBV_ILN_2064
912			\|a GBV_ILN_2244
912			\|a GBV_ILN_4046
912			\|a GBV_ILN_4266
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4309
912			\|a GBV_ILN_4311
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4314
912			\|a GBV_ILN_4315
912			\|a GBV_ILN_4317
912			\|a GBV_ILN_4318
912			\|a GBV_ILN_4319
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4700
951			\|a AR
952			\|d 20 \|j 2001 \|e 1 \|h 129-146 \|g 18

Indexfelder

author_variant	w b wb
matchkey_str	article:02780070:2001----::aesiigiecruteiiains
hierarchy_sort_str	2001
publishDate	2001
allfields	SW010313 (DE-627)OLC1600509983 (DE-599)GBVOLC1600509983 DE-627 ger DE-627 rakwb 620 Belluomini, W. verfasserin aut PAPERS - Timing - Timed Circuit Verification Using TEL Structures 2001 18 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Myers, C.J. oth Hofstee, H.P. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 1, Seite 129-146 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:1 pages:129-146 extent:18 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 1 129-146 18
spelling	SW010313 (DE-627)OLC1600509983 (DE-599)GBVOLC1600509983 DE-627 ger DE-627 rakwb 620 Belluomini, W. verfasserin aut PAPERS - Timing - Timed Circuit Verification Using TEL Structures 2001 18 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Myers, C.J. oth Hofstee, H.P. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 1, Seite 129-146 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:1 pages:129-146 extent:18 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 1 129-146 18
allfields_unstemmed	SW010313 (DE-627)OLC1600509983 (DE-599)GBVOLC1600509983 DE-627 ger DE-627 rakwb 620 Belluomini, W. verfasserin aut PAPERS - Timing - Timed Circuit Verification Using TEL Structures 2001 18 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Myers, C.J. oth Hofstee, H.P. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 1, Seite 129-146 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:1 pages:129-146 extent:18 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 1 129-146 18
allfieldsGer	SW010313 (DE-627)OLC1600509983 (DE-599)GBVOLC1600509983 DE-627 ger DE-627 rakwb 620 Belluomini, W. verfasserin aut PAPERS - Timing - Timed Circuit Verification Using TEL Structures 2001 18 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Myers, C.J. oth Hofstee, H.P. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 1, Seite 129-146 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:1 pages:129-146 extent:18 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 1 129-146 18
allfieldsSound	SW010313 (DE-627)OLC1600509983 (DE-599)GBVOLC1600509983 DE-627 ger DE-627 rakwb 620 Belluomini, W. verfasserin aut PAPERS - Timing - Timed Circuit Verification Using TEL Structures 2001 18 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Myers, C.J. oth Hofstee, H.P. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 1, Seite 129-146 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:1 pages:129-146 extent:18 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 1 129-146 18
source	Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems 20(2001), 1, Seite 129-146 volume:20 year:2001 number:1 pages:129-146 extent:18
sourceStr	Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems 20(2001), 1, Seite 129-146 volume:20 year:2001 number:1 pages:129-146 extent:18
format_phy_str_mv	Article
institution	findex.gbv.de
dewey-raw	620
isfreeaccess_bool	false
container_title	IEEE transactions on computer-aided design of integrated circuits and systems
authorswithroles_txt_mv	Belluomini, W. @@aut@@ Myers, C.J. @@oth@@ Hofstee, H.P. @@oth@@
publishDateDaySort_date	2001-01-01T00:00:00Z
hierarchy_top_id	13041705X
dewey-sort	3620
id	OLC1600509983
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC1600509983</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210701123533.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">010313s2001 xx \|\|\|\|\| 00\| \|\|und c</controlfield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">SW010313</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1600509983</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1600509983</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Belluomini, W.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">PAPERS - Timing - Timed Circuit Verification Using TEL Structures</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">18</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Myers, C.J.</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hofstee, H.P.</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on computer-aided design of integrated circuits and systems</subfield><subfield code="d">New York, NY : Institute of Electrical and Electronics Engineers, 1982</subfield><subfield code="g">20(2001), 1, Seite 129-146</subfield><subfield code="w">(DE-627)13041705X</subfield><subfield code="w">(DE-600)627344-0</subfield><subfield code="w">(DE-576)015919471</subfield><subfield code="x">0278-0070</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:20</subfield><subfield code="g">year:2001</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:129-146</subfield><subfield code="g">extent:18</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_21</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2244</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4266</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4309</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4311</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4314</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4315</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4317</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4318</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4319</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">20</subfield><subfield code="j">2001</subfield><subfield code="e">1</subfield><subfield code="h">129-146</subfield><subfield code="g">18</subfield></datafield></record></collection>
author	Belluomini, W.
spellingShingle	Belluomini, W. ddc 620 PAPERS - Timing - Timed Circuit Verification Using TEL Structures
authorStr	Belluomini, W.
ppnlink_with_tag_str_mv	@@773@@(DE-627)13041705X
format	Article
dewey-ones	620 - Engineering & allied operations
delete_txt_mv	keep
author_role	aut
collection	OLC
remote_str	false
illustrated	Not Illustrated
issn	0278-0070
topic_title	620 PAPERS - Timing - Timed Circuit Verification Using TEL Structures
topic	ddc 620
topic_unstemmed	ddc 620
topic_browse	ddc 620
format_facet	Aufsätze Gedruckte Aufsätze
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	nc
author2_variant	c m cm h h hh
hierarchy_parent_title	IEEE transactions on computer-aided design of integrated circuits and systems
hierarchy_parent_id	13041705X
dewey-tens	620 - Engineering
hierarchy_top_title	IEEE transactions on computer-aided design of integrated circuits and systems
isfreeaccess_txt	false
familylinks_str_mv	(DE-627)13041705X (DE-600)627344-0 (DE-576)015919471
title	PAPERS - Timing - Timed Circuit Verification Using TEL Structures
ctrlnum	(DE-627)OLC1600509983 (DE-599)GBVOLC1600509983
title_full	PAPERS - Timing - Timed Circuit Verification Using TEL Structures
author_sort	Belluomini, W.
journal	IEEE transactions on computer-aided design of integrated circuits and systems
journalStr	IEEE transactions on computer-aided design of integrated circuits and systems
isOA_bool	false
dewey-hundreds	600 - Technology
recordtype	marc
publishDateSort	2001
contenttype_str_mv	txt
container_start_page	129
author_browse	Belluomini, W.
container_volume	20
physical	18
class	620
format_se	Aufsätze
author-letter	Belluomini, W.
dewey-full	620
title_sort	papers - timing - timed circuit verification using tel structures
title_auth	PAPERS - Timing - Timed Circuit Verification Using TEL Structures
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700
container_issue	1
title_short	PAPERS - Timing - Timed Circuit Verification Using TEL Structures
remote_bool	false
author2	Myers, C.J. Hofstee, H.P.
author2Str	Myers, C.J. Hofstee, H.P.
ppnlink	13041705X
mediatype_str_mv	n
isOA_txt	false
hochschulschrift_bool	false
author2_role	oth oth
up_date	2024-07-03T15:22:59.074Z
_version_	1803571879290601472
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC1600509983</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210701123533.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">010313s2001 xx \|\|\|\|\| 00\| \|\|und c</controlfield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">SW010313</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1600509983</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1600509983</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Belluomini, W.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">PAPERS - Timing - Timed Circuit Verification Using TEL Structures</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">18</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Myers, C.J.</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hofstee, H.P.</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on computer-aided design of integrated circuits and systems</subfield><subfield code="d">New York, NY : Institute of Electrical and Electronics Engineers, 1982</subfield><subfield code="g">20(2001), 1, Seite 129-146</subfield><subfield code="w">(DE-627)13041705X</subfield><subfield code="w">(DE-600)627344-0</subfield><subfield code="w">(DE-576)015919471</subfield><subfield code="x">0278-0070</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:20</subfield><subfield code="g">year:2001</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:129-146</subfield><subfield code="g">extent:18</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_21</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2244</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4266</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4309</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4311</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4314</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4315</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4317</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4318</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4319</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">20</subfield><subfield code="j">2001</subfield><subfield code="e">1</subfield><subfield code="h">129-146</subfield><subfield code="g">18</subfield></datafield></record></collection>
score	7.4006567

Nicht das Richtige dabei?

Schreiben Sie uns!

PAPERS - Timing - Timed Circuit Verification Using TEL Structures

Nicht das Richtige dabei?

Zugang & Verfügbarkeit

Vorhandene Bände

Nicht das Richtige dabei?