SHORT PAPERS - A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
Autor*in: |
Ruan, S.-J. [verfasserIn] |
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Format: |
Artikel |
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Erschienen: |
2001 |
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Umfang: |
6 |
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Übergeordnetes Werk: |
Enthalten in: IEEE transactions on computer-aided design of integrated circuits and systems - New York, NY : Institute of Electrical and Electronics Engineers, 1982, 20(2001), 2, Seite 343-348 |
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Übergeordnetes Werk: |
volume:20 ; year:2001 ; number:2 ; pages:343-348 ; extent:6 |
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SW010329 (DE-627)OLC1601390467 (DE-599)GBVOLC1601390467 DE-627 ger DE-627 rakwb 620 Ruan, S.-J. verfasserin aut SHORT PAPERS - A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits 2001 6 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Shang, R.-J. oth Lai, F. oth Tsai, K.-L. oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 20(2001), 2, Seite 343-348 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:20 year:2001 number:2 pages:343-348 extent:6 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_11 GBV_ILN_20 GBV_ILN_21 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_32 GBV_ILN_62 GBV_ILN_65 GBV_ILN_70 GBV_ILN_100 GBV_ILN_120 GBV_ILN_285 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2064 GBV_ILN_2244 GBV_ILN_4046 GBV_ILN_4266 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4309 GBV_ILN_4311 GBV_ILN_4313 GBV_ILN_4314 GBV_ILN_4315 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4319 GBV_ILN_4324 GBV_ILN_4700 AR 20 2001 2 343-348 6 |
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short papers - a bipartition-codec architecture to reduce power in pipelined circuits |
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SHORT PAPERS - A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits |
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SHORT PAPERS - A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits |
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