Testing - Design of a 1.7-GHz Low-Power Delay-Fault-Testable 32-b ALU in 180-nm CMOS Technology

Gespeichert in:

Autor*in:	Chatterjee, B. [verfasserIn] Sachdev, M.

Format:	Artikel

Erschienen:	2005

Umfang:	9

Übergeordnetes Werk:	Enthalten in: IEEE transactions on very large scale integration (VLSI) systems - New York, NY : Institute of Electrical and Electronics Engineers, 1993, 13(2005), 11, Seite 1296-1304
Übergeordnetes Werk:	volume:13 ; year:2005 ; number:11 ; pages:1296-1304 ; extent:9

Katalog-ID:	OLC1691626813

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title_sort	testing - design of a 1.7-ghz low-power delay-fault-testable 32-b alu in 180-nm cmos technology
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Testing - Design of a 1.7-GHz Low-Power Delay-Fault-Testable 32-b ALU in 180-nm CMOS Technology

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