Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory

Gespeichert in:

Autor*in:	Hu, Jingtong [verfasserIn] He, Yi Zhuge, Qingfeng Sha, Edwin H.-M. Xue, Chun Jason Zhao, Yingchao

Format:	Artikel

Erschienen:	2013

Umfang:	11

Übergeordnetes Werk:	Enthalten in: Journal of systems architecture - Amsterdam [u.a.] : Elsevier, 1996, 59(2013), 7 vom: Aug., Seite 389-399
Übergeordnetes Werk:	volume:59 ; year:2013 ; number:7 ; month:08 ; pages:389-399 ; extent:11

Katalog-ID:	OLC1924797275

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allfieldsGer	sw130726_1 (DE-627)OLC1924797275 (DE-599)GBVOLC1924797275 DE-627 ger DE-627 rakwb 004 54.00 bkl Hu, Jingtong verfasserin aut Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory 2013 11 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier He, Yi oth Zhuge, Qingfeng oth Sha, Edwin H.-M. oth Xue, Chun Jason oth Zhao, Yingchao oth Enthalten in Journal of systems architecture Amsterdam [u.a.] : Elsevier, 1996 59(2013), 7 vom: Aug., Seite 389-399 (DE-627)215500083 (DE-600)1335570-3 (DE-576)054390931 1383-7621 nnns volume:59 year:2013 number:7 month:08 pages:389-399 extent:11 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_2009 54.00 AVZ AR 59 2013 7 8 389-399 11
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