A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing
This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hie...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Chenxin Zhang [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on circuits and systems / 1 - New York, NY : Institute of Electrical and Electronics Engineers, 1992, 62(2015), 3, Seite 733-742 |
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| Übergeordnetes Werk: |
volume:62 ; year:2015 ; number:3 ; pages:733-742 |
| Links: |
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| DOI / URN: |
10.1109/TCSI.2014.2366812 |
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OLC1959251147 |
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| 520 | |a This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. | ||
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10.1109/TCSI.2014.2366812 doi PQ20160617 (DE-627)OLC1959251147 (DE-599)GBVOLC1959251147 (PRQ)c2514-91c96afd602ede2ee2f63182c726243eef6a015a81736a4af2179ecfa242419c0 (KEY)0213966920150000062000300733heterogeneousreconfigurablecellarrayformimosignalp DE-627 ger DE-627 rakwb eng 000 620 DNB Chenxin Zhang verfasserin aut A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. Energy efficiency Real-time systems Real-time control Signal processing Integrated circuits Design and construction Complementary metal oxide semiconductors Usage Semiconductor chips Liang Liu oth Dejan Markovic oth Viktor Owall oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 3, Seite 733-742 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:3 pages:733-742 http://dx.doi.org/10.1109/TCSI.2014.2366812 Volltext http://search.proquest.com/docview/1660316850 http://lup.lub.lu.se/record/4857003 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 3 733-742 |
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10.1109/TCSI.2014.2366812 doi PQ20160617 (DE-627)OLC1959251147 (DE-599)GBVOLC1959251147 (PRQ)c2514-91c96afd602ede2ee2f63182c726243eef6a015a81736a4af2179ecfa242419c0 (KEY)0213966920150000062000300733heterogeneousreconfigurablecellarrayformimosignalp DE-627 ger DE-627 rakwb eng 000 620 DNB Chenxin Zhang verfasserin aut A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. Energy efficiency Real-time systems Real-time control Signal processing Integrated circuits Design and construction Complementary metal oxide semiconductors Usage Semiconductor chips Liang Liu oth Dejan Markovic oth Viktor Owall oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 3, Seite 733-742 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:3 pages:733-742 http://dx.doi.org/10.1109/TCSI.2014.2366812 Volltext http://search.proquest.com/docview/1660316850 http://lup.lub.lu.se/record/4857003 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 3 733-742 |
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10.1109/TCSI.2014.2366812 doi PQ20160617 (DE-627)OLC1959251147 (DE-599)GBVOLC1959251147 (PRQ)c2514-91c96afd602ede2ee2f63182c726243eef6a015a81736a4af2179ecfa242419c0 (KEY)0213966920150000062000300733heterogeneousreconfigurablecellarrayformimosignalp DE-627 ger DE-627 rakwb eng 000 620 DNB Chenxin Zhang verfasserin aut A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. Energy efficiency Real-time systems Real-time control Signal processing Integrated circuits Design and construction Complementary metal oxide semiconductors Usage Semiconductor chips Liang Liu oth Dejan Markovic oth Viktor Owall oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 3, Seite 733-742 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:3 pages:733-742 http://dx.doi.org/10.1109/TCSI.2014.2366812 Volltext http://search.proquest.com/docview/1660316850 http://lup.lub.lu.se/record/4857003 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 3 733-742 |
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10.1109/TCSI.2014.2366812 doi PQ20160617 (DE-627)OLC1959251147 (DE-599)GBVOLC1959251147 (PRQ)c2514-91c96afd602ede2ee2f63182c726243eef6a015a81736a4af2179ecfa242419c0 (KEY)0213966920150000062000300733heterogeneousreconfigurablecellarrayformimosignalp DE-627 ger DE-627 rakwb eng 000 620 DNB Chenxin Zhang verfasserin aut A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. Energy efficiency Real-time systems Real-time control Signal processing Integrated circuits Design and construction Complementary metal oxide semiconductors Usage Semiconductor chips Liang Liu oth Dejan Markovic oth Viktor Owall oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 3, Seite 733-742 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:3 pages:733-742 http://dx.doi.org/10.1109/TCSI.2014.2366812 Volltext http://search.proquest.com/docview/1660316850 http://lup.lub.lu.se/record/4857003 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 3 733-742 |
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10.1109/TCSI.2014.2366812 doi PQ20160617 (DE-627)OLC1959251147 (DE-599)GBVOLC1959251147 (PRQ)c2514-91c96afd602ede2ee2f63182c726243eef6a015a81736a4af2179ecfa242419c0 (KEY)0213966920150000062000300733heterogeneousreconfigurablecellarrayformimosignalp DE-627 ger DE-627 rakwb eng 000 620 DNB Chenxin Zhang verfasserin aut A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. Energy efficiency Real-time systems Real-time control Signal processing Integrated circuits Design and construction Complementary metal oxide semiconductors Usage Semiconductor chips Liang Liu oth Dejan Markovic oth Viktor Owall oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 3, Seite 733-742 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:3 pages:733-742 http://dx.doi.org/10.1109/TCSI.2014.2366812 Volltext http://search.proquest.com/docview/1660316850 http://lup.lub.lu.se/record/4857003 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 3 733-742 |
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A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing |
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A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing |
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heterogeneous reconfigurable cell array for mimo signal processing |
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A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing |
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This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. |
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This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. |
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This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 [Formula Omitted] core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 [Formula Omitted] 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. |
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A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing |
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