A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate compleme...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kishine, Keiji [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on circuits and systems / 1 - New York, NY : Institute of Electrical and Electronics Engineers, 1992, 62(2015), 5, Seite 1288-1295 |
|---|---|
| Übergeordnetes Werk: |
volume:62 ; year:2015 ; number:5 ; pages:1288-1295 |
| Links: |
|---|
| DOI / URN: |
10.1109/TCSI.2015.2416812 |
|---|
| Katalog-ID: |
OLC1959252836 |
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| 245 | 1 | 2 | |a A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS |
| 264 | 1 | |c 2015 | |
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| 520 | |a A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. | ||
| 650 | 4 | |a 65 nm CMOS | |
| 650 | 4 | |a size 65 nm | |
| 650 | 4 | |a burst data | |
| 650 | 4 | |a Integrated circuits | |
| 650 | 4 | |a symmetric loop | |
| 650 | 4 | |a multirate BCDR IC | |
| 650 | 4 | |a complementary metal oxide semiconductor | |
| 650 | 4 | |a gated voltage-controlled oscillator | |
| 650 | 4 | |a high speed | |
| 650 | 4 | |a power consumption | |
| 650 | 4 | |a burst-mode clock and data recovery circuit | |
| 650 | 4 | |a metal oxide semiconductor field effect transistor | |
| 650 | 4 | |a timing alignment | |
| 650 | 4 | |a communication IC | |
| 650 | 4 | |a Image edge detection | |
| 650 | 4 | |a instantaneous phase locking | |
| 650 | 4 | |a symmetric circuit topology | |
| 650 | 4 | |a clock and data recovery (CDR) | |
| 650 | 4 | |a AND | |
| 650 | 4 | |a clock and data recovery circuits | |
| 650 | 4 | |a GVCO | |
| 650 | 4 | |a clock signal | |
| 650 | 4 | |a Data mining | |
| 650 | 4 | |a power 60 mW | |
| 650 | 4 | |a CMOS integrated circuits | |
| 650 | 4 | |a Clocks | |
| 650 | 4 | |a CMOS | |
| 650 | 4 | |a Delays | |
| 650 | 4 | |a frequency 12.5 GHz | |
| 650 | 4 | |a MOSFET process | |
| 650 | 4 | |a precise timing adjustment | |
| 650 | 4 | |a multi-rate | |
| 650 | 4 | |a jitter | |
| 650 | 4 | |a logic gates | |
| 650 | 4 | |a Burst-mode | |
| 650 | 4 | |a voltage-controlled oscillators | |
| 650 | 4 | |a Product introduction | |
| 650 | 4 | |a Oscillators (Electronics) | |
| 650 | 4 | |a Metal oxide semiconductor field effect transistors | |
| 650 | 4 | |a Design and construction | |
| 650 | 4 | |a Complementary metal oxide semiconductors | |
| 650 | 4 | |a Semiconductor chips | |
| 650 | 4 | |a Usage | |
| 700 | 1 | |a Inaba, Hiromi |4 oth | |
| 700 | 1 | |a Inoue, Hiroshi |4 oth | |
| 700 | 1 | |a Nakamura, Makoto |4 oth | |
| 700 | 1 | |a Tsuchiya, Akira |4 oth | |
| 700 | 1 | |a Katsurai, Hiroaki |4 oth | |
| 700 | 1 | |a Onodera, Hidetoshi |4 oth | |
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| 773 | 1 | 8 | |g volume:62 |g year:2015 |g number:5 |g pages:1288-1295 |
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10.1109/TCSI.2015.2416812 doi PQ20160617 (DE-627)OLC1959252836 (DE-599)GBVOLC1959252836 (PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0 (KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf DE-627 ger DE-627 rakwb eng 000 620 DNB Kishine, Keiji verfasserin aut A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage Inaba, Hiromi oth Inoue, Hiroshi oth Nakamura, Makoto oth Tsuchiya, Akira oth Katsurai, Hiroaki oth Onodera, Hidetoshi oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 5, Seite 1288-1295 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:5 pages:1288-1295 http://dx.doi.org/10.1109/TCSI.2015.2416812 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7097115 http://search.proquest.com/docview/1685292557 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 5 1288-1295 |
| spelling |
10.1109/TCSI.2015.2416812 doi PQ20160617 (DE-627)OLC1959252836 (DE-599)GBVOLC1959252836 (PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0 (KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf DE-627 ger DE-627 rakwb eng 000 620 DNB Kishine, Keiji verfasserin aut A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage Inaba, Hiromi oth Inoue, Hiroshi oth Nakamura, Makoto oth Tsuchiya, Akira oth Katsurai, Hiroaki oth Onodera, Hidetoshi oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 5, Seite 1288-1295 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:5 pages:1288-1295 http://dx.doi.org/10.1109/TCSI.2015.2416812 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7097115 http://search.proquest.com/docview/1685292557 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 5 1288-1295 |
| allfields_unstemmed |
10.1109/TCSI.2015.2416812 doi PQ20160617 (DE-627)OLC1959252836 (DE-599)GBVOLC1959252836 (PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0 (KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf DE-627 ger DE-627 rakwb eng 000 620 DNB Kishine, Keiji verfasserin aut A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage Inaba, Hiromi oth Inoue, Hiroshi oth Nakamura, Makoto oth Tsuchiya, Akira oth Katsurai, Hiroaki oth Onodera, Hidetoshi oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 5, Seite 1288-1295 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:5 pages:1288-1295 http://dx.doi.org/10.1109/TCSI.2015.2416812 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7097115 http://search.proquest.com/docview/1685292557 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 5 1288-1295 |
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10.1109/TCSI.2015.2416812 doi PQ20160617 (DE-627)OLC1959252836 (DE-599)GBVOLC1959252836 (PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0 (KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf DE-627 ger DE-627 rakwb eng 000 620 DNB Kishine, Keiji verfasserin aut A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage Inaba, Hiromi oth Inoue, Hiroshi oth Nakamura, Makoto oth Tsuchiya, Akira oth Katsurai, Hiroaki oth Onodera, Hidetoshi oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 5, Seite 1288-1295 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:5 pages:1288-1295 http://dx.doi.org/10.1109/TCSI.2015.2416812 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7097115 http://search.proquest.com/docview/1685292557 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 5 1288-1295 |
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10.1109/TCSI.2015.2416812 doi PQ20160617 (DE-627)OLC1959252836 (DE-599)GBVOLC1959252836 (PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0 (KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf DE-627 ger DE-627 rakwb eng 000 620 DNB Kishine, Keiji verfasserin aut A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage Inaba, Hiromi oth Inoue, Hiroshi oth Nakamura, Makoto oth Tsuchiya, Akira oth Katsurai, Hiroaki oth Onodera, Hidetoshi oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 62(2015), 5, Seite 1288-1295 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:62 year:2015 number:5 pages:1288-1295 http://dx.doi.org/10.1109/TCSI.2015.2416812 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7097115 http://search.proquest.com/docview/1685292557 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 62 2015 5 1288-1295 |
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Kishine, Keiji @@aut@@ Inaba, Hiromi @@oth@@ Inoue, Hiroshi @@oth@@ Nakamura, Makoto @@oth@@ Tsuchiya, Akira @@oth@@ Katsurai, Hiroaki @@oth@@ Onodera, Hidetoshi @@oth@@ |
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Kishine, Keiji |
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Kishine, Keiji ddc 000 misc 65 nm CMOS misc size 65 nm misc burst data misc Integrated circuits misc symmetric loop misc multirate BCDR IC misc complementary metal oxide semiconductor misc gated voltage-controlled oscillator misc high speed misc power consumption misc burst-mode clock and data recovery circuit misc metal oxide semiconductor field effect transistor misc timing alignment misc communication IC misc Image edge detection misc instantaneous phase locking misc symmetric circuit topology misc clock and data recovery (CDR) misc AND misc clock and data recovery circuits misc GVCO misc clock signal misc Data mining misc power 60 mW misc CMOS integrated circuits misc Clocks misc CMOS misc Delays misc frequency 12.5 GHz misc MOSFET process misc precise timing adjustment misc multi-rate misc jitter misc logic gates misc Burst-mode misc voltage-controlled oscillators misc Product introduction misc Oscillators (Electronics) misc Metal oxide semiconductor field effect transistors misc Design and construction misc Complementary metal oxide semiconductors misc Semiconductor chips misc Usage A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS |
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000 620 DNB A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 65 nm CMOS size 65 nm burst data Integrated circuits symmetric loop multirate BCDR IC complementary metal oxide semiconductor gated voltage-controlled oscillator high speed power consumption burst-mode clock and data recovery circuit metal oxide semiconductor field effect transistor timing alignment communication IC Image edge detection instantaneous phase locking symmetric circuit topology clock and data recovery (CDR) AND clock and data recovery circuits GVCO clock signal Data mining power 60 mW CMOS integrated circuits Clocks CMOS Delays frequency 12.5 GHz MOSFET process precise timing adjustment multi-rate jitter logic gates Burst-mode voltage-controlled oscillators Product introduction Oscillators (Electronics) Metal oxide semiconductor field effect transistors Design and construction Complementary metal oxide semiconductors Semiconductor chips Usage |
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ddc 000 misc 65 nm CMOS misc size 65 nm misc burst data misc Integrated circuits misc symmetric loop misc multirate BCDR IC misc complementary metal oxide semiconductor misc gated voltage-controlled oscillator misc high speed misc power consumption misc burst-mode clock and data recovery circuit misc metal oxide semiconductor field effect transistor misc timing alignment misc communication IC misc Image edge detection misc instantaneous phase locking misc symmetric circuit topology misc clock and data recovery (CDR) misc AND misc clock and data recovery circuits misc GVCO misc clock signal misc Data mining misc power 60 mW misc CMOS integrated circuits misc Clocks misc CMOS misc Delays misc frequency 12.5 GHz misc MOSFET process misc precise timing adjustment misc multi-rate misc jitter misc logic gates misc Burst-mode misc voltage-controlled oscillators misc Product introduction misc Oscillators (Electronics) misc Metal oxide semiconductor field effect transistors misc Design and construction misc Complementary metal oxide semiconductors misc Semiconductor chips misc Usage |
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ddc 000 misc 65 nm CMOS misc size 65 nm misc burst data misc Integrated circuits misc symmetric loop misc multirate BCDR IC misc complementary metal oxide semiconductor misc gated voltage-controlled oscillator misc high speed misc power consumption misc burst-mode clock and data recovery circuit misc metal oxide semiconductor field effect transistor misc timing alignment misc communication IC misc Image edge detection misc instantaneous phase locking misc symmetric circuit topology misc clock and data recovery (CDR) misc AND misc clock and data recovery circuits misc GVCO misc clock signal misc Data mining misc power 60 mW misc CMOS integrated circuits misc Clocks misc CMOS misc Delays misc frequency 12.5 GHz misc MOSFET process misc precise timing adjustment misc multi-rate misc jitter misc logic gates misc Burst-mode misc voltage-controlled oscillators misc Product introduction misc Oscillators (Electronics) misc Metal oxide semiconductor field effect transistors misc Design and construction misc Complementary metal oxide semiconductors misc Semiconductor chips misc Usage |
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A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS |
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A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS |
| abstract |
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. |
| abstractGer |
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. |
| abstract_unstemmed |
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm 2 and 60 mW. |
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A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS |
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Inaba, Hiromi Inoue, Hiroshi Nakamura, Makoto Tsuchiya, Akira Katsurai, Hiroaki Onodera, Hidetoshi |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1959252836</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210715225531.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160206s2015 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TCSI.2015.2416812</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160617</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1959252836</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1959252836</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c2762-18940e66e71a0efe839006b0e5ecc7b84836401e82dd5a1ddf0921661b6f729d0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0213966920150000062000501288multirateburstmodecdrusingagvcowithsymmetricloopsf</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">000</subfield><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kishine, Keiji</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. 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