Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures
Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and c...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Liu, Dajiang [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on very large scale integration (VLSI) systems - New York, NY : Institute of Electrical and Electronics Engineers, 1993, 23(2015), 11, Seite 2581-2594 |
|---|---|
| Übergeordnetes Werk: |
volume:23 ; year:2015 ; number:11 ; pages:2581-2594 |
| Links: |
|---|
| DOI / URN: |
10.1109/TVLSI.2014.2371854 |
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| Katalog-ID: |
OLC1959572741 |
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| 520 | |a Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. | ||
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10.1109/TVLSI.2014.2371854 doi PQ20160617 (DE-627)OLC1959572741 (DE-599)GBVOLC1959572741 (PRQ)c1600-f9c4b257e760b3c23cd2c5ab09b0b41fcaa401f153ef32d38d394fa18b09ac0d0 (KEY)0226264920150000023001102581optimizingspatialmappingofnestedloopforcoarsegrain DE-627 ger DE-627 rakwb eng 004 620 DNB Liu, Dajiang verfasserin aut Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization Yin, Shouyi oth Peng, Yu oth Liu, Leibo oth Wei, Shaojun oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 23(2015), 11, Seite 2581-2594 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:23 year:2015 number:11 pages:2581-2594 http://dx.doi.org/10.1109/TVLSI.2014.2371854 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977969 http://search.proquest.com/docview/1729394789 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 23 2015 11 2581-2594 |
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10.1109/TVLSI.2014.2371854 doi PQ20160617 (DE-627)OLC1959572741 (DE-599)GBVOLC1959572741 (PRQ)c1600-f9c4b257e760b3c23cd2c5ab09b0b41fcaa401f153ef32d38d394fa18b09ac0d0 (KEY)0226264920150000023001102581optimizingspatialmappingofnestedloopforcoarsegrain DE-627 ger DE-627 rakwb eng 004 620 DNB Liu, Dajiang verfasserin aut Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization Yin, Shouyi oth Peng, Yu oth Liu, Leibo oth Wei, Shaojun oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 23(2015), 11, Seite 2581-2594 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:23 year:2015 number:11 pages:2581-2594 http://dx.doi.org/10.1109/TVLSI.2014.2371854 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977969 http://search.proquest.com/docview/1729394789 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 23 2015 11 2581-2594 |
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10.1109/TVLSI.2014.2371854 doi PQ20160617 (DE-627)OLC1959572741 (DE-599)GBVOLC1959572741 (PRQ)c1600-f9c4b257e760b3c23cd2c5ab09b0b41fcaa401f153ef32d38d394fa18b09ac0d0 (KEY)0226264920150000023001102581optimizingspatialmappingofnestedloopforcoarsegrain DE-627 ger DE-627 rakwb eng 004 620 DNB Liu, Dajiang verfasserin aut Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization Yin, Shouyi oth Peng, Yu oth Liu, Leibo oth Wei, Shaojun oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 23(2015), 11, Seite 2581-2594 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:23 year:2015 number:11 pages:2581-2594 http://dx.doi.org/10.1109/TVLSI.2014.2371854 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977969 http://search.proquest.com/docview/1729394789 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 23 2015 11 2581-2594 |
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10.1109/TVLSI.2014.2371854 doi PQ20160617 (DE-627)OLC1959572741 (DE-599)GBVOLC1959572741 (PRQ)c1600-f9c4b257e760b3c23cd2c5ab09b0b41fcaa401f153ef32d38d394fa18b09ac0d0 (KEY)0226264920150000023001102581optimizingspatialmappingofnestedloopforcoarsegrain DE-627 ger DE-627 rakwb eng 004 620 DNB Liu, Dajiang verfasserin aut Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization Yin, Shouyi oth Peng, Yu oth Liu, Leibo oth Wei, Shaojun oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 23(2015), 11, Seite 2581-2594 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:23 year:2015 number:11 pages:2581-2594 http://dx.doi.org/10.1109/TVLSI.2014.2371854 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977969 http://search.proquest.com/docview/1729394789 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 23 2015 11 2581-2594 |
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10.1109/TVLSI.2014.2371854 doi PQ20160617 (DE-627)OLC1959572741 (DE-599)GBVOLC1959572741 (PRQ)c1600-f9c4b257e760b3c23cd2c5ab09b0b41fcaa401f153ef32d38d394fa18b09ac0d0 (KEY)0226264920150000023001102581optimizingspatialmappingofnestedloopforcoarsegrain DE-627 ger DE-627 rakwb eng 004 620 DNB Liu, Dajiang verfasserin aut Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization Yin, Shouyi oth Peng, Yu oth Liu, Leibo oth Wei, Shaojun oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 23(2015), 11, Seite 2581-2594 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:23 year:2015 number:11 pages:2581-2594 http://dx.doi.org/10.1109/TVLSI.2014.2371854 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977969 http://search.proquest.com/docview/1729394789 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 23 2015 11 2581-2594 |
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004 620 DNB Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures loop nests polyhedral model Context Hardware Power demand Vectors coarse-grained reconfigurable architecture (CGRA) Affine transformation Arrays Optimization |
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ddc 004 misc loop nests misc polyhedral model misc Context misc Hardware misc Power demand misc Vectors misc coarse-grained reconfigurable architecture (CGRA) misc Affine transformation misc Arrays misc Optimization |
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Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures |
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Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures |
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Liu, Dajiang |
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optimizing spatial mapping of nested loop for coarse-grained reconfigurable architectures |
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Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures |
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Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. |
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Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. |
| abstract_unstemmed |
Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and back- end placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable. |
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Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures |
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Yin, Shouyi Peng, Yu Liu, Leibo Wei, Shaojun |
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