A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented usi...
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Autor*in:	Wei Deng [verfasserIn] Dongsheng Yang Ueno, Tomohiro Siriburanon, Teerachot Kondo, Satoshi Okada, Kenichi Matsuzawa, Akira

Format:	Artikel
Sprache:	Englisch

Erschienen:	2015

Schlagwörter:	PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter

Übergeordnetes Werk:	Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 50(2015), 1, Seite 68-80
Übergeordnetes Werk:	volume:50 ; year:2015 ; number:1 ; pages:68-80

Links:	Volltext Link aufrufen

DOI / URN:	10.1109/JSSC.2014.2348311

Katalog-ID:	OLC1965880681

Internformat


LEADER	01000caa a2200265 4500
001	OLC1965880681
003	DE-627
005	20210716031046.0
007	tu
008	160206s2015 xx \|\|\|\|\| 00\| \|\|eng c
024	7		\|a 10.1109/JSSC.2014.2348311 \|2 doi
028	5	2	\|a PQ20160617
035			\|a (DE-627)OLC1965880681
035			\|a (DE-599)GBVOLC1965880681
035			\|a (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280
035			\|a (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
041			\|a eng
082	0	4	\|a 620 \|q DNB
100	0		\|a Wei Deng \|e verfasserin \|4 aut
245	1	2	\|a A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
264		1	\|c 2015
336			\|a Text \|b txt \|2 rdacontent
337			\|a ohne Hilfsmittel zu benutzen \|b n \|2 rdamedia
338			\|a Band \|b nc \|2 rdacarrier
520			\|a This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
650		4	\|a PVT
650		4	\|a power 780 muW
650		4	\|a digital phase locked loops
650		4	\|a synthesizable
650		4	\|a low jitter
650		4	\|a Tuning
650		4	\|a standard cell
650		4	\|a varactors
650		4	\|a injection locked oscillators
650		4	\|a fine-resolution digital varactor
650		4	\|a Phase noise
650		4	\|a small area
650		4	\|a DAC
650		4	\|a interpolative phase coupled oscillator
650		4	\|a place-and-routed
650		4	\|a layout area
650		4	\|a digital design flow
650		4	\|a fully synthesizable all-digital PLL
650		4	\|a phase locked oscillators
650		4	\|a logic synthesis
650		4	\|a Bandwidth
650		4	\|a P&R
650		4	\|a low power
650		4	\|a digital CMOS process
650		4	\|a UHF oscillators
650		4	\|a injection-locking
650		4	\|a CMOS
650		4	\|a digital standard cells
650		4	\|a Phase locked loops
650		4	\|a digital varactor
650		4	\|a size 60 mum
650		4	\|a dual loop
650		4	\|a Layout
650		4	\|a gated edge injection locking technique
650		4	\|a digital-analogue conversion
650		4	\|a PLL
650		4	\|a RMS jitter
650		4	\|a fully synthesizable phase-locked loop
650		4	\|a AD-PLL
650		4	\|a current-output DAC
650		4	\|a edge injection
650		4	\|a CMOS digital integrated circuits
650		4	\|a gated injection
650		4	\|a current output digital-to-analog converter
700	0		\|a Dongsheng Yang \|4 oth
700	1		\|a Ueno, Tomohiro \|4 oth
700	1		\|a Siriburanon, Teerachot \|4 oth
700	1		\|a Kondo, Satoshi \|4 oth
700	1		\|a Okada, Kenichi \|4 oth
700	1		\|a Matsuzawa, Akira \|4 oth
773	0	8	\|i Enthalten in \|t IEEE journal of solid state circuits \|d New York, NY : IEEE, 1966 \|g 50(2015), 1, Seite 68-80 \|w (DE-627)129594865 \|w (DE-600)240580-5 \|w (DE-576)01508776X \|x 0018-9200 \|7 nnns
773	1	8	\|g volume:50 \|g year:2015 \|g number:1 \|g pages:68-80
856	4	1	\|u http://dx.doi.org/10.1109/JSSC.2014.2348311 \|3 Volltext
856	4	2	\|u http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_OLC
912			\|a SSG-OLC-TEC
912			\|a SSG-OLC-PHY
912			\|a GBV_ILN_70
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_4313
951			\|a AR
952			\|d 50 \|j 2015 \|e 1 \|h 68-80

Indexfelder

author_variant	w d wd
matchkey_str	article:00189200:2015----::flyyteialaliiaplihnepltvpaeopeoclaocretuptaadieeouiniia
hierarchy_sort_str	2015
publishDate	2015
allfields	10.1109/JSSC.2014.2348311 doi PQ20160617 (DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph DE-627 ger DE-627 rakwb eng 620 DNB Wei Deng verfasserin aut A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power. PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter Dongsheng Yang oth Ueno, Tomohiro oth Siriburanon, Teerachot oth Kondo, Satoshi oth Okada, Kenichi oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 1, Seite 68-80 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:1 pages:68-80 http://dx.doi.org/10.1109/JSSC.2014.2348311 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 1 68-80
spelling	10.1109/JSSC.2014.2348311 doi PQ20160617 (DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph DE-627 ger DE-627 rakwb eng 620 DNB Wei Deng verfasserin aut A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power. PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter Dongsheng Yang oth Ueno, Tomohiro oth Siriburanon, Teerachot oth Kondo, Satoshi oth Okada, Kenichi oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 1, Seite 68-80 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:1 pages:68-80 http://dx.doi.org/10.1109/JSSC.2014.2348311 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 1 68-80
allfields_unstemmed	10.1109/JSSC.2014.2348311 doi PQ20160617 (DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph DE-627 ger DE-627 rakwb eng 620 DNB Wei Deng verfasserin aut A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power. PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter Dongsheng Yang oth Ueno, Tomohiro oth Siriburanon, Teerachot oth Kondo, Satoshi oth Okada, Kenichi oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 1, Seite 68-80 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:1 pages:68-80 http://dx.doi.org/10.1109/JSSC.2014.2348311 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 1 68-80
allfieldsGer	10.1109/JSSC.2014.2348311 doi PQ20160617 (DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph DE-627 ger DE-627 rakwb eng 620 DNB Wei Deng verfasserin aut A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power. PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter Dongsheng Yang oth Ueno, Tomohiro oth Siriburanon, Teerachot oth Kondo, Satoshi oth Okada, Kenichi oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 1, Seite 68-80 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:1 pages:68-80 http://dx.doi.org/10.1109/JSSC.2014.2348311 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 1 68-80
allfieldsSound	10.1109/JSSC.2014.2348311 doi PQ20160617 (DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph DE-627 ger DE-627 rakwb eng 620 DNB Wei Deng verfasserin aut A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power. PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter Dongsheng Yang oth Ueno, Tomohiro oth Siriburanon, Teerachot oth Kondo, Satoshi oth Okada, Kenichi oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 1, Seite 68-80 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:1 pages:68-80 http://dx.doi.org/10.1109/JSSC.2014.2348311 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 1 68-80
language	English
source	Enthalten in IEEE journal of solid state circuits 50(2015), 1, Seite 68-80 volume:50 year:2015 number:1 pages:68-80
sourceStr	Enthalten in IEEE journal of solid state circuits 50(2015), 1, Seite 68-80 volume:50 year:2015 number:1 pages:68-80
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter
dewey-raw	620
isfreeaccess_bool	false
container_title	IEEE journal of solid state circuits
authorswithroles_txt_mv	Wei Deng @@aut@@ Dongsheng Yang @@oth@@ Ueno, Tomohiro @@oth@@ Siriburanon, Teerachot @@oth@@ Kondo, Satoshi @@oth@@ Okada, Kenichi @@oth@@ Matsuzawa, Akira @@oth@@
publishDateDaySort_date	2015-01-01T00:00:00Z
hierarchy_top_id	129594865
dewey-sort	3620
id	OLC1965880681
language_de	englisch
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1965880681</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716031046.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160206s2015 xx \|\|\|\|\| 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2014.2348311</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160617</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1965880681</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1965880681</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Wei Deng</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PVT</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">power 780 muW</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">synthesizable</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">low jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Tuning</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">standard cell</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">varactors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">injection locked oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fine-resolution digital varactor</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">small area</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">DAC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">interpolative phase coupled oscillator</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">place-and-routed</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">layout area</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital design flow</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fully synthesizable all-digital PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">phase locked oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">logic synthesis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">P&R</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">low power</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital CMOS process</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">UHF oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">injection-locking</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital standard cells</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital varactor</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">size 60 mum</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">dual loop</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Layout</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">gated edge injection locking technique</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital-analogue conversion</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">RMS jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fully synthesizable phase-locked loop</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">AD-PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">current-output DAC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">edge injection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS digital integrated circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">gated injection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">current output digital-to-analog converter</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Dongsheng Yang</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ueno, Tomohiro</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Siriburanon, Teerachot</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kondo, Satoshi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Okada, Kenichi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Matsuzawa, Akira</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">50(2015), 1, Seite 68-80</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:50</subfield><subfield code="g">year:2015</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:68-80</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2014.2348311</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">50</subfield><subfield code="j">2015</subfield><subfield code="e">1</subfield><subfield code="h">68-80</subfield></datafield></record></collection>
author	Wei Deng
spellingShingle	Wei Deng ddc 620 misc PVT misc power 780 muW misc digital phase locked loops misc synthesizable misc low jitter misc Tuning misc standard cell misc varactors misc injection locked oscillators misc fine-resolution digital varactor misc Phase noise misc small area misc DAC misc interpolative phase coupled oscillator misc place-and-routed misc layout area misc digital design flow misc fully synthesizable all-digital PLL misc phase locked oscillators misc logic synthesis misc Bandwidth misc P&R misc low power misc digital CMOS process misc UHF oscillators misc injection-locking misc CMOS misc digital standard cells misc Phase locked loops misc digital varactor misc size 60 mum misc dual loop misc Layout misc gated edge injection locking technique misc digital-analogue conversion misc PLL misc RMS jitter misc fully synthesizable phase-locked loop misc AD-PLL misc current-output DAC misc edge injection misc CMOS digital integrated circuits misc gated injection misc current output digital-to-analog converter A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
authorStr	Wei Deng
ppnlink_with_tag_str_mv	@@773@@(DE-627)129594865
format	Article
dewey-ones	620 - Engineering & allied operations
delete_txt_mv	keep
author_role	aut
collection	OLC
remote_str	false
illustrated	Not Illustrated
issn	0018-9200
topic_title	620 DNB A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique PVT power 780 muW digital phase locked loops synthesizable low jitter Tuning standard cell varactors injection locked oscillators fine-resolution digital varactor Phase noise small area DAC interpolative phase coupled oscillator place-and-routed layout area digital design flow fully synthesizable all-digital PLL phase locked oscillators logic synthesis Bandwidth P&R low power digital CMOS process UHF oscillators injection-locking CMOS digital standard cells Phase locked loops digital varactor size 60 mum dual loop Layout gated edge injection locking technique digital-analogue conversion PLL RMS jitter fully synthesizable phase-locked loop AD-PLL current-output DAC edge injection CMOS digital integrated circuits gated injection current output digital-to-analog converter
topic	ddc 620 misc PVT misc power 780 muW misc digital phase locked loops misc synthesizable misc low jitter misc Tuning misc standard cell misc varactors misc injection locked oscillators misc fine-resolution digital varactor misc Phase noise misc small area misc DAC misc interpolative phase coupled oscillator misc place-and-routed misc layout area misc digital design flow misc fully synthesizable all-digital PLL misc phase locked oscillators misc logic synthesis misc Bandwidth misc P&R misc low power misc digital CMOS process misc UHF oscillators misc injection-locking misc CMOS misc digital standard cells misc Phase locked loops misc digital varactor misc size 60 mum misc dual loop misc Layout misc gated edge injection locking technique misc digital-analogue conversion misc PLL misc RMS jitter misc fully synthesizable phase-locked loop misc AD-PLL misc current-output DAC misc edge injection misc CMOS digital integrated circuits misc gated injection misc current output digital-to-analog converter
topic_unstemmed	ddc 620 misc PVT misc power 780 muW misc digital phase locked loops misc synthesizable misc low jitter misc Tuning misc standard cell misc varactors misc injection locked oscillators misc fine-resolution digital varactor misc Phase noise misc small area misc DAC misc interpolative phase coupled oscillator misc place-and-routed misc layout area misc digital design flow misc fully synthesizable all-digital PLL misc phase locked oscillators misc logic synthesis misc Bandwidth misc P&R misc low power misc digital CMOS process misc UHF oscillators misc injection-locking misc CMOS misc digital standard cells misc Phase locked loops misc digital varactor misc size 60 mum misc dual loop misc Layout misc gated edge injection locking technique misc digital-analogue conversion misc PLL misc RMS jitter misc fully synthesizable phase-locked loop misc AD-PLL misc current-output DAC misc edge injection misc CMOS digital integrated circuits misc gated injection misc current output digital-to-analog converter
topic_browse	ddc 620 misc PVT misc power 780 muW misc digital phase locked loops misc synthesizable misc low jitter misc Tuning misc standard cell misc varactors misc injection locked oscillators misc fine-resolution digital varactor misc Phase noise misc small area misc DAC misc interpolative phase coupled oscillator misc place-and-routed misc layout area misc digital design flow misc fully synthesizable all-digital PLL misc phase locked oscillators misc logic synthesis misc Bandwidth misc P&R misc low power misc digital CMOS process misc UHF oscillators misc injection-locking misc CMOS misc digital standard cells misc Phase locked loops misc digital varactor misc size 60 mum misc dual loop misc Layout misc gated edge injection locking technique misc digital-analogue conversion misc PLL misc RMS jitter misc fully synthesizable phase-locked loop misc AD-PLL misc current-output DAC misc edge injection misc CMOS digital integrated circuits misc gated injection misc current output digital-to-analog converter
format_facet	Aufsätze Gedruckte Aufsätze
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	nc
author2_variant	d y dy t u tu t s ts s k sk k o ko a m am
hierarchy_parent_title	IEEE journal of solid state circuits
hierarchy_parent_id	129594865
dewey-tens	620 - Engineering
hierarchy_top_title	IEEE journal of solid state circuits
isfreeaccess_txt	false
familylinks_str_mv	(DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X
title	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
ctrlnum	(DE-627)OLC1965880681 (DE-599)GBVOLC1965880681 (PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280 (KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph
title_full	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
author_sort	Wei Deng
journal	IEEE journal of solid state circuits
journalStr	IEEE journal of solid state circuits
lang_code	eng
isOA_bool	false
dewey-hundreds	600 - Technology
recordtype	marc
publishDateSort	2015
contenttype_str_mv	txt
container_start_page	68
author_browse	Wei Deng
container_volume	50
class	620 DNB
format_se	Aufsätze
author-letter	Wei Deng
doi_str_mv	10.1109/JSSC.2014.2348311
dewey-full	620
title_sort	fully synthesizable all-digital pll with interpolative phase coupled oscillator, current-output dac, and fine-resolution digital varactor using gated edge injection technique
title_auth	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
abstract	This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
abstractGer	This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
abstract_unstemmed	This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313
container_issue	1
title_short	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
url	http://dx.doi.org/10.1109/JSSC.2014.2348311 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375
remote_bool	false
author2	Dongsheng Yang Ueno, Tomohiro Siriburanon, Teerachot Kondo, Satoshi Okada, Kenichi Matsuzawa, Akira
author2Str	Dongsheng Yang Ueno, Tomohiro Siriburanon, Teerachot Kondo, Satoshi Okada, Kenichi Matsuzawa, Akira
ppnlink	129594865
mediatype_str_mv	n
isOA_txt	false
hochschulschrift_bool	false
author2_role	oth oth oth oth oth oth
doi_str	10.1109/JSSC.2014.2348311
up_date	2024-07-03T19:30:11.421Z
_version_	1803587432136835073
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1965880681</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716031046.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160206s2015 xx \|\|\|\|\| 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2014.2348311</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160617</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1965880681</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1965880681</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c1556-718112b94abeca4cf30ab9dc0e915ec7e186b34c23298cc748a5d6c3a8fd17280</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0050684220150000050000100068fullysynthesizablealldigitalpllwithinterpolativeph</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Wei Deng</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PVT</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">power 780 muW</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">synthesizable</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">low jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Tuning</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">standard cell</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">varactors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">injection locked oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fine-resolution digital varactor</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">small area</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">DAC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">interpolative phase coupled oscillator</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">place-and-routed</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">layout area</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital design flow</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fully synthesizable all-digital PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">phase locked oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">logic synthesis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">P&R</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">low power</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital CMOS process</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">UHF oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">injection-locking</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital standard cells</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital varactor</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">size 60 mum</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">dual loop</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Layout</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">gated edge injection locking technique</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">digital-analogue conversion</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">RMS jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fully synthesizable phase-locked loop</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">AD-PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">current-output DAC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">edge injection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS digital integrated circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">gated injection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">current output digital-to-analog converter</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Dongsheng Yang</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ueno, Tomohiro</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Siriburanon, Teerachot</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kondo, Satoshi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Okada, Kenichi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Matsuzawa, Akira</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">50(2015), 1, Seite 68-80</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:50</subfield><subfield code="g">year:2015</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:68-80</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2014.2348311</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6891375</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">50</subfield><subfield code="j">2015</subfield><subfield code="e">1</subfield><subfield code="h">68-80</subfield></datafield></record></collection>
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A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

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