A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS
This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shapin...
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| Autor*in: |
Yoon, Do-Yeon [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 50(2015), 12, Seite 2880-2890 |
|---|---|
| Übergeordnetes Werk: |
volume:50 ; year:2015 ; number:12 ; pages:2880-2890 |
| Links: |
|---|
| DOI / URN: |
10.1109/JSSC.2015.2466459 |
|---|
| Katalog-ID: |
OLC1965881335 |
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| 520 | |a This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. | ||
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| 650 | 4 | |a Multi-stage noise shaping | |
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| 650 | 4 | |a Analog-to-digital converter (ADC) | |
| 650 | 4 | |a Feedforward neural networks | |
| 650 | 4 | |a Quantization (signal) | |
| 650 | 4 | |a delta-sigma | |
| 650 | 4 | |a Transfer functions | |
| 650 | 4 | |a continuous-time (CT) | |
| 650 | 4 | |a Bandwidth | |
| 650 | 4 | |a Delays | |
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| 700 | 1 | |a Lee, Hae-Seung |4 oth | |
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10.1109/JSSC.2015.2466459 doi PQ20160430 (DE-627)OLC1965881335 (DE-599)GBVOLC1965881335 (PRQ)c1079-fa70498f28317edfbf1f00f25d59cde1a8c82b0a83f869e06727e672355cd84c0 (KEY)0050684220150000050001202880continuoustimesturdymashdeltasigmamodulatorin28nmc DE-627 ger DE-627 rakwb eng 620 DNB Yoon, Do-Yeon verfasserin aut A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays Ho, Stacy oth Lee, Hae-Seung oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2880-2890 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2880-2890 http://dx.doi.org/10.1109/JSSC.2015.2466459 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7244336 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2880-2890 |
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10.1109/JSSC.2015.2466459 doi PQ20160430 (DE-627)OLC1965881335 (DE-599)GBVOLC1965881335 (PRQ)c1079-fa70498f28317edfbf1f00f25d59cde1a8c82b0a83f869e06727e672355cd84c0 (KEY)0050684220150000050001202880continuoustimesturdymashdeltasigmamodulatorin28nmc DE-627 ger DE-627 rakwb eng 620 DNB Yoon, Do-Yeon verfasserin aut A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays Ho, Stacy oth Lee, Hae-Seung oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2880-2890 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2880-2890 http://dx.doi.org/10.1109/JSSC.2015.2466459 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7244336 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2880-2890 |
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10.1109/JSSC.2015.2466459 doi PQ20160430 (DE-627)OLC1965881335 (DE-599)GBVOLC1965881335 (PRQ)c1079-fa70498f28317edfbf1f00f25d59cde1a8c82b0a83f869e06727e672355cd84c0 (KEY)0050684220150000050001202880continuoustimesturdymashdeltasigmamodulatorin28nmc DE-627 ger DE-627 rakwb eng 620 DNB Yoon, Do-Yeon verfasserin aut A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays Ho, Stacy oth Lee, Hae-Seung oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2880-2890 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2880-2890 http://dx.doi.org/10.1109/JSSC.2015.2466459 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7244336 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2880-2890 |
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10.1109/JSSC.2015.2466459 doi PQ20160430 (DE-627)OLC1965881335 (DE-599)GBVOLC1965881335 (PRQ)c1079-fa70498f28317edfbf1f00f25d59cde1a8c82b0a83f869e06727e672355cd84c0 (KEY)0050684220150000050001202880continuoustimesturdymashdeltasigmamodulatorin28nmc DE-627 ger DE-627 rakwb eng 620 DNB Yoon, Do-Yeon verfasserin aut A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays Ho, Stacy oth Lee, Hae-Seung oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2880-2890 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2880-2890 http://dx.doi.org/10.1109/JSSC.2015.2466459 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7244336 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2880-2890 |
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10.1109/JSSC.2015.2466459 doi PQ20160430 (DE-627)OLC1965881335 (DE-599)GBVOLC1965881335 (PRQ)c1079-fa70498f28317edfbf1f00f25d59cde1a8c82b0a83f869e06727e672355cd84c0 (KEY)0050684220150000050001202880continuoustimesturdymashdeltasigmamodulatorin28nmc DE-627 ger DE-627 rakwb eng 620 DNB Yoon, Do-Yeon verfasserin aut A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays Ho, Stacy oth Lee, Hae-Seung oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2880-2890 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2880-2890 http://dx.doi.org/10.1109/JSSC.2015.2466459 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7244336 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2880-2890 |
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620 DNB A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS multi-stage noise-shaping analog delay Multi-stage noise shaping Noise Analog-to-digital converter (ADC) Feedforward neural networks Quantization (signal) delta-sigma Transfer functions continuous-time (CT) Bandwidth Delays |
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ddc 620 misc multi-stage noise-shaping misc analog delay misc Multi-stage noise shaping misc Noise misc Analog-to-digital converter (ADC) misc Feedforward neural networks misc Quantization (signal) misc delta-sigma misc Transfer functions misc continuous-time (CT) misc Bandwidth misc Delays |
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ddc 620 misc multi-stage noise-shaping misc analog delay misc Multi-stage noise shaping misc Noise misc Analog-to-digital converter (ADC) misc Feedforward neural networks misc Quantization (signal) misc delta-sigma misc Transfer functions misc continuous-time (CT) misc Bandwidth misc Delays |
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ddc 620 misc multi-stage noise-shaping misc analog delay misc Multi-stage noise shaping misc Noise misc Analog-to-digital converter (ADC) misc Feedforward neural networks misc Quantization (signal) misc delta-sigma misc Transfer functions misc continuous-time (CT) misc Bandwidth misc Delays |
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A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS |
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A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS |
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Yoon, Do-Yeon |
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continuous-time sturdy-mash \delta\sigma modulator in 28 nm cmos |
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A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS |
| abstract |
This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. |
| abstractGer |
This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. |
| abstract_unstemmed |
This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1{\hbox {st}} -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency. |
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A Continuous-Time Sturdy-MASH \Delta\Sigma Modulator in 28 nm CMOS |
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